Datasheet

1. Software writes to the IC_DATA_CMD register with the data to be written (by writing a ‘0’ in bit 8).
2. Software must clear the RD_REQ and TX_ABRT interrupts (bits five and six, respectively) of the
IC_RAW_INTR_STAT register before proceeding. If the RD_REQ and/or TX_ABRT interrupts have been
masked, then clearing of the IC_RAW_INTR_STAT register will have already been performed when either the
R_RD_REQ or R_TX_ABRT bit has been read as one.
3.
The DW_apb_i2c releases the SCL and transmits the byte.
4. The master may hold the I2C bus by issuing a RESTART condition or release the bus by issuing a STOP
condition.

NOTE
Slave-Transmitter Operation for a Single Byte is not applicable in Ultra-Fast Mode as Read transfers are not
supported.
4.3.10.1.3. Slave-Receiver Operation for a Single Byte
When another I2C master device on the bus addresses the DW_apb_i2c and is sending data, the DW_apb_i2c acts as a
slave-receiver and the following steps occur:
1. The other I2C master device initiates an I2C transfer with an address that matches the DW_apb_i2c’s slave
address in the IC_SAR register.
2. The DW_apb_i2c acknowledges the sent address and recognizes the direction of the transfer to indicate that the
DW_apb_i2c is acting as a slave-receiver.
3. DW_apb_i2c receives the transmitted byte and places it in the receive buffer.

NOTE
If the Rx FIFO is completely filled with data when a byte is pushed, then the DW_apb_i2c slave holds the I2C SCL line
low until the Rx FIFO has some space, and then continues with the next read request.
1. DW_apb_i2c asserts the RX_FULL interrupt IC_RAW_INTR_STAT.RX_FULL. If the RX_FULL interrupt has been
masked, due to setting IC_INTR_MASK.M_RX_FULL register to zero or setting IC_TX_TL to a value larger than zero,
then it is recommended that a timing routine (described in Section 4.3.10.1.2) be implemented for periodic reads
of the IC_STATUS register. Reads of the IC_STATUS register, with bit 3 (RFNE) set at one, must then be treated by
software as the equivalent of the RX_FULL interrupt being asserted.
2. Software may read the byte from the IC_DATA_CMD register (bits 7:0).
3. The other master device may hold the I2C bus by issuing a RESTART condition, or release the bus by issuing a
STOP condition.
4.3.10.1.4. Slave-Transfer Operation For Bulk Transfers
In the standard I2C protocol, all transactions are single byte transactions and the programmer responds to a remote
master read request by writing one byte into the slave’s TX FIFO. When a slave (slave-transmitter) is issued with a read
request (RD_REQ) from the remote master (master-receiver), at a minimum there should be at least one entry placed
into the slave-transmitter’s TX FIFO. DW_apb_i2c is designed to handle more data in the TX FIFO so that subsequent
read requests can take that data without raising an interrupt to get more data. Ultimately, this eliminates the possibility
of significant latencies being incurred between raising the interrupt for data each time had there been a restriction of
having only one entry placed in the TX FIFO. This mode only occurs when DW_apb_i2c is acting as a slave-transmitter. If
the remote master acknowledges the data sent by the slave-transmitter and there is no data in the slave’s TX FIFO, the
DW_apb_i2c holds the I2C SCL line low while it raises the read request interrupt (RD_REQ) and waits for data to be
written into the TX FIFO before it can be sent to the remote master.
RP2040 Datasheet
4.3. I2C 474