Datasheet


NOTE
Depending on the reset values chosen, steps two, three, four, and five may not be necessary because the reset
values can be configured. The values stored are static and do not need to be reprogrammed if the DW_apb_i2c is
disabled, with the exception of the transfer direction and data.
4.3.10.2.2. Master Transmit and Master Receive
The DW_apb_i2c supports switching back and forth between reading and writing dynamically. To transmit data, write
the data to be written to the lower byte of the I2C Rx/Tx Data Buffer and Command Register (IC_DATA_CMD). The CMD
bit [8] should be written to zero for I2C write operations. Subsequently, a read command may be issued by writing “don’t
cares” to the lower byte of the IC_DATA_CMD register, and a one should be written to the CMD bit. The DW_apb_i2c
master continues to initiate transfers as long as there are commands present in the transmit FIFO. If the transmit FIFO
becomes empty the master either inserts a STOP condition after completing the current transfers.
•
If set to one, it issues a STOP condition after completing the current transfer.
•
If set to zero, it holds SCL low until next command is written to the transmit FIFO.
For more details, refer to Section 4.3.7.
4.3.10.3. Disabling DW_apb_i2c
The register IC_ENABLE_STATUS is added to allow software to unambiguously determine when the hardware has
completely shutdown in response to IC_ENABLE.ENABLE being set from one to zero.
Only one register is required to be monitored, as opposed to monitoring two registers (IC_STATUS and
IC_RAW_INTR_STAT) which was a requirement for earlier versions of DW_apb_i2c.

NOTE
The DW_apb_i2c Master can be disabled only if the current command being processed—when the ic_enable de-
assertion occurs—has the STOP bit set to one. When an attempt is made to disable the DW_apb_i2c Master while
processing a command without the STOP bit set, the DW_apb_i2c Master continues to remain active, holding the SCL
line low until a new command is received in the Tx FIFO. When the DW_apb_i2c Master is processing a command
without the STOP bit set, you can issue the ABORT (IC_ENABLE.ABORT) to relinquish the I2C bus and then disable
DW_apb_i2c.
4.3.10.3.1. Procedure
1. Define a timer interval (t i2c_poll ) equal to the 10 times the signalling period for the highest I2C transfer speed
used in the system and supported by DW_apb_i2c. For example, if the highest I2C transfer mode is 400 kb/s, then
this t i2c_poll is 25μs.
2. Define a maximum time-out parameter, MAX_T_POLL_COUNT, such that if any repeated polling operation exceeds
this maximum value, an error is reported.
3. Execute a blocking thread/process/function that prevents any further I2C master transactions to be started by
software, but allows any pending transfers to be completed.
RP2040 Datasheet
4.3. I2C 476