Datasheet

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NOTE
This step can be ignored if DW_apb_i2c is programmed to operate as an I2C slave only.
1. The variable POLL_COUNT is initialized to zero.
2. Set bit zero of the IC_ENABLE register to zero.
3. Read the IC_ENABLE_STATUS register and test the IC_EN bit (bit 0). Increment POLL_COUNT by one. If
POLL_COUNT >= MAX_T_POLL_COUNT, exit with the relevant error code.
4. If IC_ENABLE_STATUS[0] is one, then sleep for t i2c_poll and proceed to the previous step. Otherwise, exit with
a relevant success code.
4.3.10.4. Aborting I2C Transfers
The ABORT control bit of the IC_ENABLE register allows the software to relinquish the I2C bus before completing the
issued transfer commands from the Tx FIFO. In response to an ABORT request, the controller issues the STOP condition
over the I2C bus, followed by Tx FIFO flush. Aborting the transfer is allowed only in master mode of operation.
4.3.10.4.1. Procedure
1. Stop filling the Tx FIFO (IC_DATA_CMD) with new commands.
2. When operating in DMA mode, disable the transmit DMA by setting TDMAE to zero.
3. Set IC_ENABLE.ABORT to one.
4. Wait for the M_TX_ABRT interrupt.
5. Read the IC_TX_ABRT_SOURCE register to identify the source as ABRT_USER_ABRT.
4.3.11. Spike Suppression
The DW_apb_i2c contains programmable spike suppression logic that match requirements imposed by the I2C Bus
Specification for SS/FS modes. This logic is based on counters that monitor the input signals (SCL and SDA), checking if
they remain stable for a predetermined amount of ic_clk cycles before they are sampled internally. There is one
separate counter for each signal (SCL and SDA). The number of ic_clk cycles can be programmed by the user and should
be calculated taking into account the frequency of ic_clk and the relevant spike length specification. Each counter is
started whenever its input signal changes its value. Depending on the behaviour of the input signal, one of the following
scenarios occurs:
•
The input signal remains unchanged until the counter reaches its count limit value. When this happens, the internal
version of the signal is updated with the input value, and the counter is reset and stopped. The counter is not
restarted until a new change on the input signal is detected.
•
The input signal changes again before the counter reaches its count limit value. When this happens, the counter is
reset and stopped, but the internal version of the signal is not updated. The counter remains stopped until a new
change on the input signal is detected.
The timing diagram in Figure 83 illustrates the behaviour described above.
Recovery Clocks
Spike length counter
SCL
Internal filtered SCL
0 1 2 3 0 1 2 3 4 5 0
Figure 83. Spike
Suppression Example
RP2040 Datasheet
4.3. I2C 477