Datasheet

Table 24. GPIO_OE
Register
Bits Description Type Reset
31:30 Reserved. - -
29:0
Set output enable (1/0 → output/input) for GPIO0…29.
Reading back gives the last value written.
If core 0 and core 1 both write to GPIO_OE simultaneously (or to a
SET/CLR/XOR alias),
the result is as though the write from core 0 took place first,
and the write from core 1 was then applied to that intermediate result.
RW 0x00000000
SIO: GPIO_OE_SET Register
Offset: 0x024
Description
GPIO output enable set
Table 25.
GPIO_OE_SET Register
Bits Description Type Reset
31:30 Reserved. - -
29:0
Perform an atomic bit-set on GPIO_OE, i.e. GPIO_OE |= wdata
RW 0x00000000
SIO: GPIO_OE_CLR Register
Offset: 0x028
Description
GPIO output enable clear
Table 26.
GPIO_OE_CLR Register
Bits Description Type Reset
31:30 Reserved. - -
29:0
Perform an atomic bit-clear on GPIO_OE, i.e. GPIO_OE &= ~wdata
RW 0x00000000
SIO: GPIO_OE_XOR Register
Offset: 0x02c
Description
GPIO output enable XOR
Table 27.
GPIO_OE_XOR
Register
Bits Description Type Reset
31:30 Reserved. - -
29:0
Perform an atomic bitwise XOR on GPIO_OE, i.e. GPIO_OE ^= wdata
RW 0x00000000
SIO: GPIO_HI_OUT Register
Offset: 0x030
Description
QSPI output value
RP2040 Datasheet
2.3. Processor subsystem 47