Datasheet

1. Master sends a maximum of nine clock pulses to recover the bus LOW within those nine clocks.
◦
The number of clock pulses will vary with the number of bits that remain to be sent by the slave. As the
maximum number of bits is nine, master sends up to nine clock pluses and allows the slave to recover it.
◦
The master attempts to assert a Logic 1 on the SDA line and check whether SDA is recovered. If the SDA is not
recovered, it will continue to send a maximum of nine SCL clocks.
2.
If SDA line is recovered within nine clock pulses then the master will send the STOP to release the bus.
3.
If SDA line is not recovered even after the ninth clock pulse then system needs a hardware reset.
Recovery Clocks
SDA
SCL
MST_SDA
0 1 2 3 4 5 6 7 8 9 10
Master drives 9 clocks to recover SDA stuck at low
Figure 84. SDA
Recovery with 9 SCL
Clocks
Recovery Clocks
SDA
SCL
MST_SDA
0 1 2 3 4 5 6 7
Master drives 9 clocks to recover SDA stuck at low
Figure 85. SDA
Recovery with 6 SCL
Clocks
4.3.13.2. SCL Line is Stuck at LOW
In the unlikely event (due to an electric failure of a circuit) where the clock (SCL) is stuck to LOW, there is no effective
method to overcome this problem but to reset the bus using the hardware reset signal.
4.3.14. IC_CLK Frequency Configuration
When the DW_apb_i2c is configured as a Standard (SS), Fast (FS)/Fast-Mode Plus (FM+), the *CNT registers must be
set before any I2C bus transaction can take place in order to ensure proper I/O timing. The *CNT registers are:
•
IC_SS_SCL_HCNT
•
IC_SS_SCL_LCNT
•
IC_FS_SCL_HCNT
•
IC_FS_SCL_LCNT

NOTE
The tBUF timing and setup/hold time of START, STOP and RESTART registers uses *HCNT/*LCNT register settings
for the corresponding speed mode.

NOTE
It is not necessary to program any of the *CNT registers if the DW_apb_i2c is enabled to operate only as an I2C
slave, since these registers are used only to determine the SCL timing requirements for operation as an I2C master.
Table 459 lists the derivation of I2C timing parameters from the *CNT programming registers.
Table 459. Derivation
of I2C Timing
Parameters from
*CNT Registers
Timing Parameter Symbol Standard Speed Fast Speed / Fast Speed Plus
LOW period of the SCL clock
tLOW IC_SS_SCL_LCNT IC_FS_SCL_LCNT
RP2040 Datasheet
4.3. I2C 479