Datasheet

SCL_PERIOD_FS / (IC_HCNT_FS + IC_LCNT_FS) = IC_CLK_PERIOD
IC_LCNT_FS × IC_CLK_PERIOD = MIN_SCL_LOWtime_FS
Combined, the previous equations produce the following:
IC_LCNT_FS × (SCL_PERIOD_FS / (IC_LCNT_FS + IC_HCNT_FS) ) = MIN_SCL_LOWtime_FS
Solving for IC_LCNT_FS:
IC_LCNT_FS × (2.5μs / (IC_LCNT_FS + 14) ) = 1.3μs
The previous equation gives:
IC_LCNT_FS = roundup(15.166) = 16
These calculations produce IC_LCNT_FS = 16 and IC_HCNT_FS = 14, giving an ic_clk value of:
2.5 μs / (16 + 14) = 83.3ns = 12MHz
Testing these results shows that protocol requirements are satisfied.
Table 460 lists the minimum ic_clk values for all modes with high and low count values.
Table 460. ic_clk in
Relation to High and
Low Counts
Speed Mode ic_clkfreq
(MHz)
Minimum
Value of
IC_*_SPKLEN
SCL Low
Time in
`ic_clk`s
SCL Low
Program
Value
SCL Low
Time
SCL High
Time in
`ic_clk`s
SCL High
Program
Value
SCL High
Time
SS 2.7 1 13 12 4.7 µs 14 6 5.2 µs
FS 12.0 1 16 15 1.33 µs 14 6 1.16 µs
FM+ 32 2 16 15 500 ns 16 7 500 ns
•
The IC_*_SCL_LCNT and IC_*_SCL_HCNT registers are programmed using the SCL low and high program values in
Table 460, which are calculated using SCL low count minus one, and SCL high counts minus eight, respectively. The
values in Table 460 are based on IC_SDA_RX_HOLD = 0. The maximum IC_SDA_RX_HOLD value depends on the
IC_*CNT registers in Master mode.
•
In order to compute the HCNT and LCNT considering RC timings, use the following equations:
◦
IC_HCNT_* = [(HCNT + IC_*_SPKLEN + 7) * ic_clk] + SCL_Fall_time
◦
IC_LCNT_* = [(LCNT + 1) * ic_clk] - SCL_Fall_time + SCL_Rise_time
4.3.14.3. Calculating High and Low Counts
The calculations below show how to calculate SCL high and low counts for each speed mode in the DW_apb_i2c. For the
calculations to work, the ic_clk frequencies used must not be less than the minimum ic_clk frequencies specified in
Table 460.
The default ic_clk period value is set to 100ns, so default SCL high and low count values are calculated for each speed
RP2040 Datasheet
4.3. I2C 482