Datasheet

mode based on this clock. These values need updating according to the guidelines below.
The equation to calculate the proper number of ic_clk signals required for setting the proper SCL clocks high and low
times is as follows:
Ê IC_xCNT = (ROUNDUP(MIN_SCL_xxxtime*OSCFREQ,0))
Ê MIN_SCL_HIGHtime = Minimum High Period
Ê MIN_SCL_HIGHtime = 4000 ns for 100 kbps,
Ê 600 ns for 400 kbps,
Ê 260 ns for 1000 kbps,
Ê MIN_SCL_LOWtime = Minimum Low Period
Ê MIN_SCL_LOWtime = 4700 ns for 100 kbps,
Ê 1300 ns for 400 kbps,
Ê 500 ns for 1000 kbps,
Ê OSCFREQ = ic_clk Clock Frequency (Hz).
For example:
Ê OSCFREQ = 100 MHz
Ê I2Cmode = fast, 400 kbit/s
Ê MIN_SCL_HIGHtime = 600 ns.
Ê MIN_SCL_LOWtime = 1300 ns.
Ê IC_xCNT = (ROUNDUP(MIN_SCL_HIGH_LOWtime*OSCFREQ,0))
Ê IC_HCNT = (ROUNDUP(600 ns * 100 MHz,0))
Ê IC_HCNTSCL PERIOD = 60
Ê IC_LCNT = (ROUNDUP(1300 ns * 100 MHz,0))
Ê IC_LCNTSCL PERIOD = 130
Ê Actual MIN_SCL_HIGHtime = 60*(1/100 MHz) = 600 ns
Ê Actual MIN_SCL_LOWtime = 130*(1/100 MHz) = 1300 ns
4.3.15. DMA Controller Interface
The DW_apb_i2c has built-in DMA capability; it has a handshaking interface to the DMA Controller to request and control
transfers. The APB bus is used to perform the data transfer to or from the DMA. DMA transfers are transferred as single
accesses as data rate is relatively low.
4.3.15.1. Enabling the DMA Controller Interface
To enable the DMA Controller interface on the DW_apb_i2c, you must write the DMA Control Register (IC_DMA_CR).
Writing a one into the TDMAE bit field of IC_DMA_CR register enables the DW_apb_i2c transmit handshaking interface.
Writing a one into the RDMAE bit field of the IC_DMA_CR register enables the DW_apb_i2c receive handshaking
interface.
4.3.15.2. Overview of Operation
The DMA Controller is programmed with the number of data items (transfer count) that are to be transmitted or
received by DW_apb_i2c.
The transfer is broken into single transfers on the bus, each initiated by a request from the DW_apb_i2c.
RP2040 Datasheet
4.3. I2C 483