Datasheet

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For example, where the transfer count programmed into the DMA Controller is four. The DMA transfer consists of a

series of four single transactions. If the DW_apb_i2c makes a transmit request to this channel, a single data item is

written to the DW_apb_i2c TX FIFO. Similarly, if the DW_apb_i2c makes a receive request to this channel, a single data

item is read from the DW_apb_i2c RX FIFO. Four separate requests must be made to this DMA channel before all four

data items are written or read.

4.3.15.3. Watermark Levels

In DW_apb_i2c the registers for setting watermarks to allow DMA bursts do not need be set to anything other than their

reset value. Specifically IC_DMA_TDLR and IC_DMA_RDLR can be left at reset values of zero. This is because only single

transfers are needed due to the low bandwidth of I2C relative to system bandwidth, and also the DMA controller

normally has highest priority on the system bus so will generally complete very quickly.

4.3.16. Operation of Interrupt Registers

Table 461 lists the operation of the DW_apb_i2c interrupt registers and how they are set and cleared. Some bits are set

by hardware and cleared by software, whereas other bits are set and cleared by hardware.

Table 461. Clearing

and Setting of

Interrupt Registers

Interrupt Bit Fields Set by Hardware/Cleared by Software Set and Cleared by Hardware

MST_ON_HOLD N Y

RESTART_DET Y N

GEN_CALL Y N

START_DET Y N

STOP_DET Y N

ACTIVITY Y N

RX_DONE Y N

TX_ABRT Y N

RD_REQ Y N

TX_EMPTY N Y

TX_OVER Y N

RX_FULL N Y

RX_OVER Y N

RX_UNDER Y N

4.3.17. List of Registers

The I2C0 and I2C1 registers start at base addresses of 0x40044000 and 0x40048000 respectively (defined as I2C0_BASE