Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.5. DMA
- 2.6. Memory
- 2.7. Boot Sequence
- 2.8. Bootrom
- 2.9. Power Supplies
- 2.10. Core Supply Regulator
- 2.11. Power Control
- 2.12. Chip-Level Reset
- 2.13. Power-On State Machine
- 2.14. Subsystem Resets
- 2.15. Clocks
- 2.16. Crystal Oscillator (XOSC)
- 2.17. Ring Oscillator (ROSC)
- 2.18. PLL
- 2.19. GPIO
- 2.20. Sysinfo
- 2.21. Syscfg
- 2.22. TBMAN
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. UART
- 4.3. I2C
- 4.3.1. Features
- 4.3.2. IP Configuration
- 4.3.3. I2C Overview
- 4.3.4. I2C Terminology
- 4.3.5. I2C Behaviour
- 4.3.6. I2C Protocols
- 4.3.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.3.8. Multiple Master Arbitration
- 4.3.9. Clock Synchronization
- 4.3.10. Operation Modes
- 4.3.11. Spike Suppression
- 4.3.12. Fast Mode Plus Operation
- 4.3.13. Bus Clear Feature
- 4.3.14. IC_CLK Frequency Configuration
- 4.3.15. DMA Controller Interface
- 4.3.16. Operation of Interrupt Registers
- 4.3.17. List of Registers
- 4.4. SPI
- 4.5. PWM
- 4.6. Timer
- 4.7. Watchdog
- 4.8. RTC
- 4.9. ADC and Temperature Sensor
- 4.10. SSI
- 4.10.1. Overview
- 4.10.2. Features
- 4.10.3. IP Modifications
- 4.10.4. Clock Ratios
- 4.10.5. Transmit and Receive FIFO Buffers
- 4.10.6. 32-Bit Frame Size Support
- 4.10.7. SSI Interrupts
- 4.10.8. Transfer Modes
- 4.10.9. Operation Modes
- 4.10.10. Partner Connection Interfaces
- 4.10.11. DMA Controller Interface
- 4.10.12. APB Interface
- 4.10.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
- Appendix C: Documentation Release History
Offset Name Info
0x14 IC_SS_SCL_HCNT Standard Speed I2C Clock SCL High Count Register
0x18 IC_SS_SCL_LCNT Standard Speed I2C Clock SCL Low Count Register
0x1c IC_FS_SCL_HCNT Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register
0x20 IC_FS_SCL_LCNT Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register
0x2c IC_INTR_STAT I2C Interrupt Status Register
0x30 IC_INTR_MASK I2C Interrupt Mask Register
0x34 IC_RAW_INTR_STAT I2C Raw Interrupt Status Register
0x38 IC_RX_TL I2C Receive FIFO Threshold Register
0x3c IC_TX_TL I2C Transmit FIFO Threshold Register
0x40 IC_CLR_INTR Clear Combined and Individual Interrupt Register
0x44 IC_CLR_RX_UNDER Clear RX_UNDER Interrupt Register
0x48 IC_CLR_RX_OVER Clear RX_OVER Interrupt Register
0x4c IC_CLR_TX_OVER Clear TX_OVER Interrupt Register
0x50 IC_CLR_RD_REQ Clear RD_REQ Interrupt Register
0x54 IC_CLR_TX_ABRT Clear TX_ABRT Interrupt Register
0x58 IC_CLR_RX_DONE Clear RX_DONE Interrupt Register
0x5c IC_CLR_ACTIVITY Clear ACTIVITY Interrupt Register
0x60 IC_CLR_STOP_DET Clear STOP_DET Interrupt Register
0x64 IC_CLR_START_DET Clear START_DET Interrupt Register
0x68 IC_CLR_GEN_CALL Clear GEN_CALL Interrupt Register
0x6c IC_ENABLE I2C ENABLE Register
0x70 IC_STATUS I2C STATUS Register
0x74 IC_TXFLR I2C Transmit FIFO Level Register
0x78 IC_RXFLR I2C Receive FIFO Level Register
0x7c IC_SDA_HOLD I2C SDA Hold Time Length Register
0x80 IC_TX_ABRT_SOURCE I2C Transmit Abort Source Register
0x84 IC_SLV_DATA_NACK_ONLY Generate Slave Data NACK Register
0x88 IC_DMA_CR DMA Control Register
0x8c IC_DMA_TDLR DMA Transmit Data Level Register
0x90 IC_DMA_RDLR DMA Transmit Data Level Register
0x94 IC_SDA_SETUP I2C SDA Setup Register
0x98 IC_ACK_GENERAL_CALL I2C ACK General Call Register
0x9c IC_ENABLE_STATUS I2C Enable Status Register
0xa0 IC_FS_SPKLEN I2C SS, FS or FM+ spike suppression limit
0xa8 IC_CLR_RESTART_DET Clear RESTART_DET Interrupt Register
0xf4 IC_COMP_PARAM_1 Component Parameter Register 1
RP2040 Datasheet
4.3. I2C 485