Datasheet

Offset Name Info
0xf8 IC_COMP_VERSION I2C Component Version Register
0xfc IC_COMP_TYPE I2C Component Type Register
I2C: IC_CON Register
Offset: 0x00
Description
I2C Control Register. This register can be written only when the DW_apb_i2c is disabled, which corresponds to the
IC_ENABLE[0] register being set to 0. Writes at other times have no effect.
Read/Write Access: - bit 10 is read only. - bit 11 is read only - bit 16 is read only - bit 17 is read only - bits 18 and 19 are
read only.
Table 463. IC_CON
Register
Bits Name Description Type Reset
31:11 Reserved. - - -
10 STOP_DET_IF_MA
STER_ACTIVE
Master issues the STOP_DET interrupt irrespective of
whether master is active or not
RO 0x0
9 RX_FIFO_FULL_HL
D_CTRL
This bit controls whether DW_apb_i2c should hold the bus
when the Rx FIFO is physically full to its
RX_BUFFER_DEPTH, as described in the
IC_RX_FULL_HLD_BUS_EN parameter.
Reset value: 0x0.
0x0 → Overflow when RX_FIFO is full
0x1 → Hold bus when RX_FIFO is full
RW 0x0
8 TX_EMPTY_CTRL This bit controls the generation of the TX_EMPTY
interrupt, as described in the IC_RAW_INTR_STAT register.
Reset value: 0x0.
0x0 → Default behaviour of TX_EMPTY interrupt
0x1 → Controlled generation of TX_EMPTY interrupt
RW 0x0
7 STOP_DET_IFADD
RESSED
In slave mode: - 1’b1: issues the STOP_DET interrupt only
when it is addressed. - 1’b0: issues the STOP_DET
irrespective of whether it’s addressed or not. Reset value:
0x0
NOTE: During a general call address, this slave does not
issue the STOP_DET interrupt if
STOP_DET_IF_ADDRESSED = 1’b1, even if the slave
responds to the general call address by generating ACK.
The STOP_DET interrupt is generated only when the
transmitted address matches the slave address (SAR).
0x0 → slave issues STOP_DET intr always
0x1 → slave issues STOP_DET intr only if addressed
RW 0x0
RP2040 Datasheet
4.3. I2C 486