Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.5. DMA
- 2.6. Memory
- 2.7. Boot Sequence
- 2.8. Bootrom
- 2.9. Power Supplies
- 2.10. Core Supply Regulator
- 2.11. Power Control
- 2.12. Chip-Level Reset
- 2.13. Power-On State Machine
- 2.14. Subsystem Resets
- 2.15. Clocks
- 2.16. Crystal Oscillator (XOSC)
- 2.17. Ring Oscillator (ROSC)
- 2.18. PLL
- 2.19. GPIO
- 2.20. Sysinfo
- 2.21. Syscfg
- 2.22. TBMAN
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. UART
- 4.3. I2C
- 4.3.1. Features
- 4.3.2. IP Configuration
- 4.3.3. I2C Overview
- 4.3.4. I2C Terminology
- 4.3.5. I2C Behaviour
- 4.3.6. I2C Protocols
- 4.3.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.3.8. Multiple Master Arbitration
- 4.3.9. Clock Synchronization
- 4.3.10. Operation Modes
- 4.3.11. Spike Suppression
- 4.3.12. Fast Mode Plus Operation
- 4.3.13. Bus Clear Feature
- 4.3.14. IC_CLK Frequency Configuration
- 4.3.15. DMA Controller Interface
- 4.3.16. Operation of Interrupt Registers
- 4.3.17. List of Registers
- 4.4. SPI
- 4.5. PWM
- 4.6. Timer
- 4.7. Watchdog
- 4.8. RTC
- 4.9. ADC and Temperature Sensor
- 4.10. SSI
- 4.10.1. Overview
- 4.10.2. Features
- 4.10.3. IP Modifications
- 4.10.4. Clock Ratios
- 4.10.5. Transmit and Receive FIFO Buffers
- 4.10.6. 32-Bit Frame Size Support
- 4.10.7. SSI Interrupts
- 4.10.8. Transfer Modes
- 4.10.9. Operation Modes
- 4.10.10. Partner Connection Interfaces
- 4.10.11. DMA Controller Interface
- 4.10.12. APB Interface
- 4.10.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
- Appendix C: Documentation Release History
Bits Name Description Type Reset
6 IC_SLAVE_DISABL
E
This bit controls whether I2C has its slave disabled, which
means once the presetn signal is applied, then this bit is
set and the slave is disabled.
If this bit is set (slave is disabled), DW_apb_i2c functions
only as a master and does not perform any action that
requires a slave.
NOTE: Software should ensure that if this bit is written
with 0, then bit 0 should also be written with a 0.
0x0 → Slave mode is enabled
0x1 → Slave mode is disabled
RW 0x1
5 IC_RESTART_EN Determines whether RESTART conditions may be sent
when acting as a master. Some older slaves do not
support handling RESTART conditions; however, RESTART
conditions are used in several DW_apb_i2c operations.
When RESTART is disabled, the master is prohibited from
performing the following functions: - Sending a START
BYTE - Performing any high-speed mode operation - High-
speed mode operation - Performing direction changes in
combined format mode - Performing a read operation with
a 10-bit address By replacing RESTART condition followed
by a STOP and a subsequent START condition, split
operations are broken down into multiple DW_apb_i2c
transfers. If the above operations are performed, it will
result in setting bit 6 (TX_ABRT) of the
IC_RAW_INTR_STAT register.
Reset value: ENABLED
0x0 → Master restart disabled
0x1 → Master restart enabled
RW 0x1
4 IC_10BITADDR_M
ASTER
Controls whether the DW_apb_i2c starts its transfers in 7-
or 10-bit addressing mode when acting as a master. - 0: 7-
bit addressing - 1: 10-bit addressing
0x0 → Master 7Bit addressing mode
0x1 → Master 10Bit addressing mode
RW 0x0
3 IC_10BITADDR_SL
AVE
When acting as a slave, this bit controls whether the
DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit
addressing. The DW_apb_i2c ignores transactions that
involve 10-bit addressing; for 7-bit addressing, only the
lower 7 bits of the IC_SAR register are compared. - 1: 10-
bit addressing. The DW_apb_i2c responds to only 10-bit
addressing transfers that match the full 10 bits of the
IC_SAR register.
0x0 → Slave 7Bit addressing
0x1 → Slave 10Bit addressing
RW 0x0
RP2040 Datasheet
4.3. I2C 487