Datasheet

Table 28.
GPIO_HI_OUT Register
Bits Description Type Reset
31:6 Reserved. - -
5:0
Set output level (1/0 → high/low) for QSPI IO0…5.
Reading back gives the last value written, NOT the input value from the pins.
If core 0 and core 1 both write to GPIO_HI_OUT simultaneously (or to a
SET/CLR/XOR alias),
the result is as though the write from core 0 took place first,
and the write from core 1 was then applied to that intermediate result.
RW 0x00
SIO: GPIO_HI_OUT_SET Register
Offset: 0x034
Description
QSPI output value set
Table 29.
GPIO_HI_OUT_SET
Register
Bits Description Type Reset
31:6 Reserved. - -
5:0
Perform an atomic bit-set on GPIO_HI_OUT, i.e. GPIO_HI_OUT |= wdata
RW 0x00
SIO: GPIO_HI_OUT_CLR Register
Offset: 0x038
Description
QSPI output value clear
Table 30.
GPIO_HI_OUT_CLR
Register
Bits Description Type Reset
31:6 Reserved. - -
5:0
Perform an atomic bit-clear on GPIO_HI_OUT, i.e. GPIO_HI_OUT &= ~wdata
RW 0x00
SIO: GPIO_HI_OUT_XOR Register
Offset: 0x03c
Description
QSPI output value XOR
Table 31.
GPIO_HI_OUT_XOR
Register
Bits Description Type Reset
31:6 Reserved. - -
5:0
Perform an atomic bitwise XOR on GPIO_HI_OUT, i.e. GPIO_HI_OUT ^= wdata
RW 0x00
SIO: GPIO_HI_OE Register
Offset: 0x040
Description
QSPI output enable
RP2040 Datasheet
2.3. Processor subsystem 48