Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.5. DMA
- 2.6. Memory
- 2.7. Boot Sequence
- 2.8. Bootrom
- 2.9. Power Supplies
- 2.10. Core Supply Regulator
- 2.11. Power Control
- 2.12. Chip-Level Reset
- 2.13. Power-On State Machine
- 2.14. Subsystem Resets
- 2.15. Clocks
- 2.16. Crystal Oscillator (XOSC)
- 2.17. Ring Oscillator (ROSC)
- 2.18. PLL
- 2.19. GPIO
- 2.20. Sysinfo
- 2.21. Syscfg
- 2.22. TBMAN
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. UART
- 4.3. I2C
- 4.3.1. Features
- 4.3.2. IP Configuration
- 4.3.3. I2C Overview
- 4.3.4. I2C Terminology
- 4.3.5. I2C Behaviour
- 4.3.6. I2C Protocols
- 4.3.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.3.8. Multiple Master Arbitration
- 4.3.9. Clock Synchronization
- 4.3.10. Operation Modes
- 4.3.11. Spike Suppression
- 4.3.12. Fast Mode Plus Operation
- 4.3.13. Bus Clear Feature
- 4.3.14. IC_CLK Frequency Configuration
- 4.3.15. DMA Controller Interface
- 4.3.16. Operation of Interrupt Registers
- 4.3.17. List of Registers
- 4.4. SPI
- 4.5. PWM
- 4.6. Timer
- 4.7. Watchdog
- 4.8. RTC
- 4.9. ADC and Temperature Sensor
- 4.10. SSI
- 4.10.1. Overview
- 4.10.2. Features
- 4.10.3. IP Modifications
- 4.10.4. Clock Ratios
- 4.10.5. Transmit and Receive FIFO Buffers
- 4.10.6. 32-Bit Frame Size Support
- 4.10.7. SSI Interrupts
- 4.10.8. Transfer Modes
- 4.10.9. Operation Modes
- 4.10.10. Partner Connection Interfaces
- 4.10.11. DMA Controller Interface
- 4.10.12. APB Interface
- 4.10.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
- Appendix C: Documentation Release History
Bits Name Description Type Reset
9 STOP This bit controls whether a STOP is issued after the byte is
sent or received.
- 1 - STOP is issued after this byte, regardless of whether
or not the Tx FIFO is empty. If the Tx FIFO is not empty,
the master immediately tries to start a new transfer by
issuing a START and arbitrating for the bus. - 0 - STOP is
not issued after this byte, regardless of whether or not the
Tx FIFO is empty. If the Tx FIFO is not empty, the master
continues the current transfer by sending/receiving data
bytes according to the value of the CMD bit. If the Tx FIFO
is empty, the master holds the SCL line low and stalls the
bus until a new command is available in the Tx FIFO.
Reset value: 0x0
0x0 → Don’t Issue STOP after this command
0x1 → Issue STOP after this command
SC 0x0
8 CMD This bit controls whether a read or a write is performed.
This bit does not control the direction when the
DW_apb_i2con acts as a slave. It controls only the
direction when it acts as a master.
When a command is entered in the TX FIFO, this bit
distinguishes the write and read commands. In slave-
receiver mode, this bit is a 'don’t care' because writes to
this register are not required. In slave-transmitter mode, a
'0' indicates that the data in IC_DATA_CMD is to be
transmitted.
When programming this bit, you should remember the
following: attempting to perform a read operation after a
General Call command has been sent results in a
TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT
register), unless bit 11 (SPECIAL) in the IC_TAR register
has been cleared. If a '1' is written to this bit after
receiving a RD_REQ interrupt, then a TX_ABRT interrupt
occurs.
Reset value: 0x0
0x0 → Master Write Command
0x1 → Master Read Command
SC 0x0
7:0 DAT This register contains the data to be transmitted or
received on the I2C bus. If you are writing to this register
and want to perform a read, bits 7:0 (DAT) are ignored by
the DW_apb_i2c. However, when you read this register,
these bits return the value of data received on the
DW_apb_i2c interface.
Reset value: 0x0
RW 0x00
I2C: IC_SS_SCL_HCNT Register
Offset: 0x14
RP2040 Datasheet
4.3. I2C 492