Datasheet

Table 32. GPIO_HI_OE
Register
Bits Description Type Reset
31:6 Reserved. - -
5:0
Set output enable (1/0 → output/input) for QSPI IO0…5.
Reading back gives the last value written.
If core 0 and core 1 both write to GPIO_HI_OE simultaneously (or to a
SET/CLR/XOR alias),
the result is as though the write from core 0 took place first,
and the write from core 1 was then applied to that intermediate result.
RW 0x00
SIO: GPIO_HI_OE_SET Register
Offset: 0x044
Description
QSPI output enable set
Table 33.
GPIO_HI_OE_SET
Register
Bits Description Type Reset
31:6 Reserved. - -
5:0
Perform an atomic bit-set on GPIO_HI_OE, i.e. GPIO_HI_OE |= wdata
RW 0x00
SIO: GPIO_HI_OE_CLR Register
Offset: 0x048
Description
QSPI output enable clear
Table 34.
GPIO_HI_OE_CLR
Register
Bits Description Type Reset
31:6 Reserved. - -
5:0
Perform an atomic bit-clear on GPIO_HI_OE, i.e. GPIO_HI_OE &= ~wdata
RW 0x00
SIO: GPIO_HI_OE_XOR Register
Offset: 0x04c
Description
QSPI output enable XOR
Table 35.
GPIO_HI_OE_XOR
Register
Bits Description Type Reset
31:6 Reserved. - -
5:0
Perform an atomic bitwise XOR on GPIO_HI_OE, i.e. GPIO_HI_OE ^= wdata
RW 0x00
SIO: FIFO_ST Register
Offset: 0x050
Description
Status register for inter-core FIFOs (mailboxes).
There is one FIFO in the core 0 → core 1 direction, and one core 1 → core 0. Both are 32 bits wide and 8 words
deep.
Core 0 can see the read side of the 1→0 FIFO (RX), and the write side of 0→1 FIFO (TX).
Core 1 can see the read side of the 0→1 FIFO (RX), and the write side of 1→0 FIFO (TX).
The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register.
RP2040 Datasheet
2.3. Processor subsystem 49