Datasheet

Bits Name Description Type Reset
6 TX_ABRT This bit indicates if DW_apb_i2c, as an I2C transmitter, is
unable to complete the intended actions on the contents
of the transmit FIFO. This situation can occur both as an
I2C master or an I2C slave, and is referred to as a 'transmit
abort'. When this bit is set to 1, the IC_TX_ABRT_SOURCE
register indicates the reason why the transmit abort takes
places.
Note: The DW_apb_i2c flushes/resets/empties the
TX_FIFO and RX_FIFO whenever there is a transmit abort
caused by any of the events tracked by the
IC_TX_ABRT_SOURCE register. The FIFOs remains in this
flushed state until the register IC_CLR_TX_ABRT is read.
Once this read is performed, the Tx FIFO is then ready to
accept more data bytes from the APB interface.
Reset value: 0x0
0x0 → TX_ABRT interrupt is inactive
0x1 → TX_ABRT interrupt is active
RO 0x0
5 RD_REQ This bit is set to 1 when DW_apb_i2c is acting as a slave
and another I2C master is attempting to read data from
DW_apb_i2c. The DW_apb_i2c holds the I2C bus in a wait
state (SCL=0) until this interrupt is serviced, which means
that the slave has been addressed by a remote master
that is asking for data to be transferred. The processor
must respond to this interrupt and then write the
requested data to the IC_DATA_CMD register. This bit is
set to 0 just after the processor reads the IC_CLR_RD_REQ
register.
Reset value: 0x0
0x0 → RD_REQ interrupt is inactive
0x1 → RD_REQ interrupt is active
RO 0x0
4 TX_EMPTY The behavior of the TX_EMPTY interrupt status differs
based on the TX_EMPTY_CTRL selection in the IC_CON
register. - When TX_EMPTY_CTRL = 0: This bit is set to 1
when the transmit buffer is at or below the threshold value
set in the IC_TX_TL register. - When TX_EMPTY_CTRL = 1:
This bit is set to 1 when the transmit buffer is at or below
the threshold value set in the IC_TX_TL register and the
transmission of the address/data from the internal shift
register for the most recently popped command is
completed. It is automatically cleared by hardware when
the buffer level goes above the threshold. When
IC_ENABLE[0] is set to 0, the TX FIFO is flushed and held
in reset. There the TX FIFO looks like it has no data within
it, so this bit is set to 1, provided there is activity in the
master or slave state machines. When there is no longer
any activity, then with ic_en=0, this bit is set to 0.
Reset value: 0x0.
0x0 → TX_EMPTY interrupt is inactive
0x1 → TX_EMPTY interrupt is active
RO 0x0
RP2040 Datasheet
4.3. I2C 501