Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.5. DMA
- 2.6. Memory
- 2.7. Boot Sequence
- 2.8. Bootrom
- 2.9. Power Supplies
- 2.10. Core Supply Regulator
- 2.11. Power Control
- 2.12. Chip-Level Reset
- 2.13. Power-On State Machine
- 2.14. Subsystem Resets
- 2.15. Clocks
- 2.16. Crystal Oscillator (XOSC)
- 2.17. Ring Oscillator (ROSC)
- 2.18. PLL
- 2.19. GPIO
- 2.20. Sysinfo
- 2.21. Syscfg
- 2.22. TBMAN
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. UART
- 4.3. I2C
- 4.3.1. Features
- 4.3.2. IP Configuration
- 4.3.3. I2C Overview
- 4.3.4. I2C Terminology
- 4.3.5. I2C Behaviour
- 4.3.6. I2C Protocols
- 4.3.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.3.8. Multiple Master Arbitration
- 4.3.9. Clock Synchronization
- 4.3.10. Operation Modes
- 4.3.11. Spike Suppression
- 4.3.12. Fast Mode Plus Operation
- 4.3.13. Bus Clear Feature
- 4.3.14. IC_CLK Frequency Configuration
- 4.3.15. DMA Controller Interface
- 4.3.16. Operation of Interrupt Registers
- 4.3.17. List of Registers
- 4.4. SPI
- 4.5. PWM
- 4.6. Timer
- 4.7. Watchdog
- 4.8. RTC
- 4.9. ADC and Temperature Sensor
- 4.10. SSI
- 4.10.1. Overview
- 4.10.2. Features
- 4.10.3. IP Modifications
- 4.10.4. Clock Ratios
- 4.10.5. Transmit and Receive FIFO Buffers
- 4.10.6. 32-Bit Frame Size Support
- 4.10.7. SSI Interrupts
- 4.10.8. Transfer Modes
- 4.10.9. Operation Modes
- 4.10.10. Partner Connection Interfaces
- 4.10.11. DMA Controller Interface
- 4.10.12. APB Interface
- 4.10.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
- Appendix C: Documentation Release History
Bits Name Description Type Reset
1 ABORT When set, the controller initiates the transfer abort. - 0:
ABORT not initiated or ABORT done - 1: ABORT operation
in progress The software can abort the I2C transfer in
master mode by setting this bit. The software can set this
bit only when ENABLE is already set; otherwise, the
controller ignores any write to ABORT bit. The software
cannot clear the ABORT bit once set. In response to an
ABORT, the controller issues a STOP and flushes the Tx
FIFO after completing the current transfer, then sets the
TX_ABORT interrupt after the abort operation. The ABORT
bit is cleared automatically after the abort operation.
For a detailed description on how to abort I2C transfers,
refer to 'Aborting I2C Transfers'.
Reset value: 0x0
0x0 → ABORT operation not in progress
0x1 → ABORT operation in progress
RW 0x0
0 ENABLE Controls whether the DW_apb_i2c is enabled. - 0: Disables
DW_apb_i2c (TX and RX FIFOs are held in an erased state)
- 1: Enables DW_apb_i2c Software can disable
DW_apb_i2c while it is active. However, it is important that
care be taken to ensure that DW_apb_i2c is disabled
properly. A recommended procedure is described in
'Disabling DW_apb_i2c'.
When DW_apb_i2c is disabled, the following occurs: - The
TX FIFO and RX FIFO get flushed. - Status bits in the
IC_INTR_STAT register are still active until DW_apb_i2c
goes into IDLE state. If the module is transmitting, it stops
as well as deletes the contents of the transmit buffer after
the current transfer is complete. If the module is receiving,
the DW_apb_i2c stops the current transfer at the end of
the current byte and does not acknowledge the transfer.
In systems with asynchronous pclk and ic_clk when
IC_CLK_TYPE parameter set to asynchronous (1), there is
a two ic_clk delay when enabling or disabling the
DW_apb_i2c. For a detailed description on how to disable
DW_apb_i2c, refer to 'Disabling DW_apb_i2c'
Reset value: 0x0
0x0 → I2C is disabled
0x1 → I2C is enabled
RW 0x0
I2C: IC_STATUS Register
Offset: 0x70
Description
I2C Status Register
This is a read-only register used to indicate the current transfer status and FIFO status. The status register may be read
at any time. None of the bits in this register request an interrupt.
RP2040 Datasheet
4.3. I2C 508