Datasheet

Table 36. FIFO_ST
Register
Bits Name Description Type Reset
31:4 Reserved. - - -
3 ROE Sticky flag indicating the RX FIFO was read when empty.
This read was ignored by the FIFO.
WC 0x0
2 WOF Sticky flag indicating the TX FIFO was written when full.
This write was ignored by the FIFO.
WC 0x0
1 RDY Value is 1 if this core’s TX FIFO is not full (i.e. if FIFO_WR
is ready for more data)
RO 0x1
0 VLD Value is 1 if this core’s RX FIFO is not empty (i.e. if
FIFO_RD is valid)
RO 0x0
SIO: FIFO_WR Register
Offset: 0x054
Table 37. FIFO_WR
Register
Bits Description Type Reset
31:0 Write access to this core’s TX FIFO WF 0x00000000
SIO: FIFO_RD Register
Offset: 0x058
Table 38. FIFO_RD
Register
Bits Description Type Reset
31:0 Read access to this core’s RX FIFO RF -
SIO: SPINLOCK_ST Register
Offset: 0x05c
Table 39.
SPINLOCK_ST
Register
Bits Description Type Reset
31:0 Spinlock state
A bitmap containing the state of all 32 spinlocks (1=locked).
Mainly intended for debugging.
RO 0x00000000
SIO: DIV_UDIVIDEND Register
Offset: 0x060
Table 40.
DIV_UDIVIDEND
Register
Bits Description Type Reset
31:0 Divider unsigned dividend
Write to the DIVIDEND operand of the divider, i.e. the p in p / q.
Any operand write starts a new calculation. The results appear in QUOTIENT,
REMAINDER.
UDIVIDEND/SDIVIDEND are aliases of the same internal register. The U alias
starts an
unsigned calculation, and the S alias starts a signed calculation.
RW 0x00000000
SIO: DIV_UDIVISOR Register
Offset: 0x064
RP2040 Datasheet
2.3. Processor subsystem 50