Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.5. DMA
- 2.6. Memory
- 2.7. Boot Sequence
- 2.8. Bootrom
- 2.9. Power Supplies
- 2.10. Core Supply Regulator
- 2.11. Power Control
- 2.12. Chip-Level Reset
- 2.13. Power-On State Machine
- 2.14. Subsystem Resets
- 2.15. Clocks
- 2.16. Crystal Oscillator (XOSC)
- 2.17. Ring Oscillator (ROSC)
- 2.18. PLL
- 2.19. GPIO
- 2.20. Sysinfo
- 2.21. Syscfg
- 2.22. TBMAN
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. UART
- 4.3. I2C
- 4.3.1. Features
- 4.3.2. IP Configuration
- 4.3.3. I2C Overview
- 4.3.4. I2C Terminology
- 4.3.5. I2C Behaviour
- 4.3.6. I2C Protocols
- 4.3.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.3.8. Multiple Master Arbitration
- 4.3.9. Clock Synchronization
- 4.3.10. Operation Modes
- 4.3.11. Spike Suppression
- 4.3.12. Fast Mode Plus Operation
- 4.3.13. Bus Clear Feature
- 4.3.14. IC_CLK Frequency Configuration
- 4.3.15. DMA Controller Interface
- 4.3.16. Operation of Interrupt Registers
- 4.3.17. List of Registers
- 4.4. SPI
- 4.5. PWM
- 4.6. Timer
- 4.7. Watchdog
- 4.8. RTC
- 4.9. ADC and Temperature Sensor
- 4.10. SSI
- 4.10.1. Overview
- 4.10.2. Features
- 4.10.3. IP Modifications
- 4.10.4. Clock Ratios
- 4.10.5. Transmit and Receive FIFO Buffers
- 4.10.6. 32-Bit Frame Size Support
- 4.10.7. SSI Interrupts
- 4.10.8. Transfer Modes
- 4.10.9. Operation Modes
- 4.10.10. Partner Connection Interfaces
- 4.10.11. DMA Controller Interface
- 4.10.12. APB Interface
- 4.10.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
- Appendix C: Documentation Release History
Bits Name Description Type Reset
15 ABRT_SLVRD_INT
X
1: When the processor side responds to a slave mode
request for data to be transmitted to a remote master and
user writes a 1 in CMD (bit 8) of IC_DATA_CMD register.
Reset value: 0x0
Role of DW_apb_i2c: Slave-Transmitter
0x0 → Slave trying to transmit to remote master in read
mode- scenario not present
0x1 → Slave trying to transmit to remote master in read
mode
RO 0x0
14 ABRT_SLV_ARBL
OST
This field indicates that a Slave has lost the bus while
transmitting data to a remote master.
IC_TX_ABRT_SOURCE[12] is set at the same time. Note:
Even though the slave never 'owns' the bus, something
could go wrong on the bus. This is a fail safe check. For
instance, during a data transmission at the low-to-high
transition of SCL, if what is on the data bus is not what is
supposed to be transmitted, then DW_apb_i2c no longer
own the bus.
Reset value: 0x0
Role of DW_apb_i2c: Slave-Transmitter
0x0 → Slave lost arbitration to remote master- scenario
not present
0x1 → Slave lost arbitration to remote master
RO 0x0
13 ABRT_SLVFLUSH_
TXFIFO
This field specifies that the Slave has received a read
command and some data exists in the TX FIFO, so the
slave issues a TX_ABRT interrupt to flush old data in TX
FIFO.
Reset value: 0x0
Role of DW_apb_i2c: Slave-Transmitter
0x0 → Slave flushes existing data in TX-FIFO upon getting
read command- scenario not present
0x1 → Slave flushes existing data in TX-FIFO upon getting
read command
RO 0x0
12 ARB_LOST This field specifies that the Master has lost arbitration, or
if IC_TX_ABRT_SOURCE[14] is also set, then the slave
transmitter has lost arbitration.
Reset value: 0x0
Role of DW_apb_i2c: Master-Transmitter or Slave-
Transmitter
0x0 → Master or Slave-Transmitter lost arbitration-
scenario not present
0x1 → Master or Slave-Transmitter lost arbitration
RO 0x0
RP2040 Datasheet
4.3. I2C 512