Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.5. DMA
- 2.6. Memory
- 2.7. Boot Sequence
- 2.8. Bootrom
- 2.9. Power Supplies
- 2.10. Core Supply Regulator
- 2.11. Power Control
- 2.12. Chip-Level Reset
- 2.13. Power-On State Machine
- 2.14. Subsystem Resets
- 2.15. Clocks
- 2.16. Crystal Oscillator (XOSC)
- 2.17. Ring Oscillator (ROSC)
- 2.18. PLL
- 2.19. GPIO
- 2.20. Sysinfo
- 2.21. Syscfg
- 2.22. TBMAN
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. UART
- 4.3. I2C
- 4.3.1. Features
- 4.3.2. IP Configuration
- 4.3.3. I2C Overview
- 4.3.4. I2C Terminology
- 4.3.5. I2C Behaviour
- 4.3.6. I2C Protocols
- 4.3.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.3.8. Multiple Master Arbitration
- 4.3.9. Clock Synchronization
- 4.3.10. Operation Modes
- 4.3.11. Spike Suppression
- 4.3.12. Fast Mode Plus Operation
- 4.3.13. Bus Clear Feature
- 4.3.14. IC_CLK Frequency Configuration
- 4.3.15. DMA Controller Interface
- 4.3.16. Operation of Interrupt Registers
- 4.3.17. List of Registers
- 4.4. SPI
- 4.5. PWM
- 4.6. Timer
- 4.7. Watchdog
- 4.8. RTC
- 4.9. ADC and Temperature Sensor
- 4.10. SSI
- 4.10.1. Overview
- 4.10.2. Features
- 4.10.3. IP Modifications
- 4.10.4. Clock Ratios
- 4.10.5. Transmit and Receive FIFO Buffers
- 4.10.6. 32-Bit Frame Size Support
- 4.10.7. SSI Interrupts
- 4.10.8. Transfer Modes
- 4.10.9. Operation Modes
- 4.10.10. Partner Connection Interfaces
- 4.10.11. DMA Controller Interface
- 4.10.12. APB Interface
- 4.10.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
- Appendix C: Documentation Release History
Bits Name Description Type Reset
11 ABRT_MASTER_DI
S
This field indicates that the User tries to initiate a Master
operation with the Master mode disabled.
Reset value: 0x0
Role of DW_apb_i2c: Master-Transmitter or Master-
Receiver
0x0 → User initiating master operation when MASTER
disabled- scenario not present
0x1 → User initiating master operation when MASTER
disabled
RO 0x0
10 ABRT_10B_RD_N
ORSTRT
This field indicates that the restart is disabled
(IC_RESTART_EN bit (IC_CON[5]) =0) and the master
sends a read command in 10-bit addressing mode.
Reset value: 0x0
Role of DW_apb_i2c: Master-Receiver
0x0 → Master not trying to read in 10Bit addressing mode
when RESTART disabled
0x1 → Master trying to read in 10Bit addressing mode
when RESTART disabled
RO 0x0
9 ABRT_SBYTE_NO
RSTRT
To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT
must be fixed first; restart must be enabled (IC_CON[5]=1),
the SPECIAL bit must be cleared (IC_TAR[11]), or the
GC_OR_START bit must be cleared (IC_TAR[10]). Once the
source of the ABRT_SBYTE_NORSTRT is fixed, then this
bit can be cleared in the same manner as other bits in this
register. If the source of the ABRT_SBYTE_NORSTRT is
not fixed before attempting to clear this bit, bit 9 clears for
one cycle and then gets reasserted. When this field is set
to 1, the restart is disabled (IC_RESTART_EN bit
(IC_CON[5]) =0) and the user is trying to send a START
Byte.
Reset value: 0x0
Role of DW_apb_i2c: Master
0x0 → User trying to send START byte when RESTART
disabled- scenario not present
0x1 → User trying to send START byte when RESTART
disabled
RO 0x0
RP2040 Datasheet
4.3. I2C 513