Datasheet

A write can occur on this register if both of the following conditions are met: - DW_apb_i2c is disabled (IC_ENABLE[0] =
0) - Slave part is inactive (IC_STATUS[6] = 0) Note: The IC_STATUS[6] is a register read-back location for the internal
slv_activity signal; the user should poll this before writing the ic_slv_data_nack_only bit.
Table 493.
IC_SLV_DATA_NACK_
ONLY Register
Bits Name Description Type Reset
31:1 Reserved. - - -
0 NACK Generate NACK. This NACK generation only occurs when
DW_apb_i2c is a slave-receiver. If this register is set to a
value of 1, it can only generate a NACK after a data byte is
received; hence, the data transfer is aborted and the data
received is not pushed to the receive buffer.
When the register is set to a value of 0, it generates
NACK/ACK, depending on normal criteria. - 1: generate
NACK after data byte received - 0: generate NACK/ACK
normally Reset value: 0x0
0x0 → Slave receiver generates NACK normally
0x1 → Slave receiver generates NACK upon data
reception only
RW 0x0
I2C: IC_DMA_CR Register
Offset: 0x88
Description
DMA Control Register
The register is used to enable the DMA Controller interface operation. There is a separate bit for transmit and receive.
This can be programmed regardless of the state of IC_ENABLE.
Table 494.
IC_DMA_CR Register
Bits Name Description Type Reset
31:2 Reserved. - - -
1 TDMAE Transmit DMA Enable. This bit enables/disables the
transmit FIFO DMA channel. Reset value: 0x0
0x0 → transmit FIFO DMA channel disabled
0x1 → Transmit FIFO DMA channel enabled
RW 0x0
0 RDMAE Receive DMA Enable. This bit enables/disables the receive
FIFO DMA channel. Reset value: 0x0
0x0 → Receive FIFO DMA channel disabled
0x1 → Receive FIFO DMA channel enabled
RW 0x0
I2C: IC_DMA_TDLR Register
Offset: 0x8c
Description
DMA Transmit Data Level Register
RP2040 Datasheet
4.3. I2C 516