Datasheet

Table 41.
DIV_UDIVISOR
Register
Bits Description Type Reset
31:0 Divider unsigned divisor
Write to the DIVISOR operand of the divider, i.e. the q in p / q.
Any operand write starts a new calculation. The results appear in QUOTIENT,
REMAINDER.
UDIVIDEND/SDIVIDEND are aliases of the same internal register. The U alias
starts an
unsigned calculation, and the S alias starts a signed calculation.
RW 0x00000000
SIO: DIV_SDIVIDEND Register
Offset: 0x068
Table 42.
DIV_SDIVIDEND
Register
Bits Description Type Reset
31:0 Divider signed dividend
The same as UDIVIDEND, but starts a signed calculation, rather than unsigned.
RW 0x00000000
SIO: DIV_SDIVISOR Register
Offset: 0x06c
Table 43.
DIV_SDIVISOR
Register
Bits Description Type Reset
31:0 Divider signed divisor
The same as UDIVISOR, but starts a signed calculation, rather than unsigned.
RW 0x00000000
SIO: DIV_QUOTIENT Register
Offset: 0x070
Table 44.
DIV_QUOTIENT
Register
Bits Description Type Reset
31:0 Divider result quotient
The result of DIVIDEND / DIVISOR (division). Contents undefined while
CSR_READY is low.
For signed calculations, QUOTIENT is negative when the signs of DIVIDEND
and DIVISOR differ.
This register can be written to directly, for context save/restore purposes. This
halts any
in-progress calculation and sets the CSR_READY and CSR_DIRTY flags.
Reading from QUOTIENT clears the CSR_DIRTY flag, so should read results in
the order
REMAINDER, QUOTIENT if CSR_DIRTY is used.
RW 0x00000000
SIO: DIV_REMAINDER Register
Offset: 0x074
RP2040 Datasheet
2.3. Processor subsystem 51