Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.5. DMA
- 2.6. Memory
- 2.7. Boot Sequence
- 2.8. Bootrom
- 2.9. Power Supplies
- 2.10. Core Supply Regulator
- 2.11. Power Control
- 2.12. Chip-Level Reset
- 2.13. Power-On State Machine
- 2.14. Subsystem Resets
- 2.15. Clocks
- 2.16. Crystal Oscillator (XOSC)
- 2.17. Ring Oscillator (ROSC)
- 2.18. PLL
- 2.19. GPIO
- 2.20. Sysinfo
- 2.21. Syscfg
- 2.22. TBMAN
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. UART
- 4.3. I2C
- 4.3.1. Features
- 4.3.2. IP Configuration
- 4.3.3. I2C Overview
- 4.3.4. I2C Terminology
- 4.3.5. I2C Behaviour
- 4.3.6. I2C Protocols
- 4.3.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.3.8. Multiple Master Arbitration
- 4.3.9. Clock Synchronization
- 4.3.10. Operation Modes
- 4.3.11. Spike Suppression
- 4.3.12. Fast Mode Plus Operation
- 4.3.13. Bus Clear Feature
- 4.3.14. IC_CLK Frequency Configuration
- 4.3.15. DMA Controller Interface
- 4.3.16. Operation of Interrupt Registers
- 4.3.17. List of Registers
- 4.4. SPI
- 4.5. PWM
- 4.6. Timer
- 4.7. Watchdog
- 4.8. RTC
- 4.9. ADC and Temperature Sensor
- 4.10. SSI
- 4.10.1. Overview
- 4.10.2. Features
- 4.10.3. IP Modifications
- 4.10.4. Clock Ratios
- 4.10.5. Transmit and Receive FIFO Buffers
- 4.10.6. 32-Bit Frame Size Support
- 4.10.7. SSI Interrupts
- 4.10.8. Transfer Modes
- 4.10.9. Operation Modes
- 4.10.10. Partner Connection Interfaces
- 4.10.11. DMA Controller Interface
- 4.10.12. APB Interface
- 4.10.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
- Appendix C: Documentation Release History
Bits Name Description Type Reset
1 SLV_DISABLED_W
HILE_BUSY
Slave Disabled While Busy (Transmit, Receive). This bit
indicates if a potential or active Slave operation has been
aborted due to the setting bit 0 of the IC_ENABLE register
from 1 to 0. This bit is set when the CPU writes a 0 to the
IC_ENABLE register while:
(a) DW_apb_i2c is receiving the address byte of the Slave-
Transmitter operation from a remote master;
OR,
(b) address and data bytes of the Slave-Receiver operation
from a remote master.
When read as 1, DW_apb_i2c is deemed to have forced a
NACK during any part of an I2C transfer, irrespective of
whether the I2C address matches the slave address set in
DW_apb_i2c (IC_SAR register) OR if the transfer is
completed before IC_ENABLE is set to 0 but has not taken
effect.
Note: If the remote I2C master terminates the transfer
with a STOP condition before the DW_apb_i2c has a
chance to NACK a transfer, and IC_ENABLE[0] has been
set to 0, then this bit will also be set to 1.
When read as 0, DW_apb_i2c is deemed to have been
disabled when there is master activity, or when the I2C
bus is idle.
Note: The CPU can safely read this bit when IC_EN (bit 0)
is read as 0.
Reset value: 0x0
0x0 → Slave is disabled when it is idle
0x1 → Slave is disabled when it is active
RO 0x0
0 IC_EN ic_en Status. This bit always reflects the value driven on
the output port ic_en. - When read as 1, DW_apb_i2c is
deemed to be in an enabled state. - When read as 0,
DW_apb_i2c is deemed completely inactive. Note: The
CPU can safely read this bit anytime. When this bit is read
as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2)
and SLV_DISABLED_WHILE_BUSY (bit 1).
Reset value: 0x0
0x0 → I2C disabled
0x1 → I2C enabled
RO 0x0
I2C: IC_FS_SPKLEN Register
Offset: 0xa0
RP2040 Datasheet
4.3. I2C 520