Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.5. DMA
- 2.6. Memory
- 2.7. Boot Sequence
- 2.8. Bootrom
- 2.9. Power Supplies
- 2.10. Core Supply Regulator
- 2.11. Power Control
- 2.12. Chip-Level Reset
- 2.13. Power-On State Machine
- 2.14. Subsystem Resets
- 2.15. Clocks
- 2.16. Crystal Oscillator (XOSC)
- 2.17. Ring Oscillator (ROSC)
- 2.18. PLL
- 2.19. GPIO
- 2.20. Sysinfo
- 2.21. Syscfg
- 2.22. TBMAN
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. UART
- 4.3. I2C
- 4.3.1. Features
- 4.3.2. IP Configuration
- 4.3.3. I2C Overview
- 4.3.4. I2C Terminology
- 4.3.5. I2C Behaviour
- 4.3.6. I2C Protocols
- 4.3.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.3.8. Multiple Master Arbitration
- 4.3.9. Clock Synchronization
- 4.3.10. Operation Modes
- 4.3.11. Spike Suppression
- 4.3.12. Fast Mode Plus Operation
- 4.3.13. Bus Clear Feature
- 4.3.14. IC_CLK Frequency Configuration
- 4.3.15. DMA Controller Interface
- 4.3.16. Operation of Interrupt Registers
- 4.3.17. List of Registers
- 4.4. SPI
- 4.5. PWM
- 4.6. Timer
- 4.7. Watchdog
- 4.8. RTC
- 4.9. ADC and Temperature Sensor
- 4.10. SSI
- 4.10.1. Overview
- 4.10.2. Features
- 4.10.3. IP Modifications
- 4.10.4. Clock Ratios
- 4.10.5. Transmit and Receive FIFO Buffers
- 4.10.6. 32-Bit Frame Size Support
- 4.10.7. SSI Interrupts
- 4.10.8. Transfer Modes
- 4.10.9. Operation Modes
- 4.10.10. Partner Connection Interfaces
- 4.10.11. DMA Controller Interface
- 4.10.12. APB Interface
- 4.10.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
- Appendix C: Documentation Release History
Description
I2C SS, FS or FM+ spike suppression limit
This register is used to store the duration, measured in ic_clk cycles, of the longest spike that is filtered out by the spike
suppression logic when the component is operating in SS, FS or FM+ modes. The relevant I2C requirement is tSP (table
4) as detailed in the I2C Bus Specification. This register must be programmed with a minimum value of 1.
Table 500.
IC_FS_SPKLEN
Register
Bits Name Description Type Reset
31:8 Reserved. - - -
7:0 IC_FS_SPKLEN This register must be set before any I2C bus transaction
can take place to ensure stable operation. This register
sets the duration, measured in ic_clk cycles, of the longest
spike in the SCL or SDA lines that will be filtered out by the
spike suppression logic. This register can be written only
when the I2C interface is disabled which corresponds to
the IC_ENABLE[0] register being set to 0. Writes at other
times have no effect. The minimum valid value is 1;
hardware prevents values less than this being written, and
if attempted results in 1 being set. or more information,
refer to 'Spike Suppression'.
RW 0x07
I2C: IC_CLR_RESTART_DET Register
Offset: 0xa8
Description
Clear RESTART_DET Interrupt Register
Table 501.
IC_CLR_RESTART_DET
Register
Bits Name Description Type Reset
31:1 Reserved. - - -
0 CLR_RESTART_DE
T
Read this register to clear the RESTART_DET interrupt (bit
12) of IC_RAW_INTR_STAT register.
Reset value: 0x0
RO 0x0
I2C: IC_COMP_PARAM_1 Register
Offset: 0xf4
Description
Component Parameter Register 1
Note This register is not implemented and therefore reads as 0. If it was implemented it would be a constant read-only
register that contains encoded information about the component’s parameter settings. Fields shown below are the
settings for those parameters
Table 502.
IC_COMP_PARAM_1
Register
Bits Name Description Type Reset
31:24 Reserved. - - -
23:16 TX_BUFFER_DEPT
H
TX Buffer Depth = 16 RO 0x00
15:8 RX_BUFFER_DEPT
H
RX Buffer Depth = 16 RO 0x00
7 ADD_ENCODED_P
ARAMS
Encoded parameters not visible RO 0x0
RP2040 Datasheet
4.3. I2C 521