Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.5. DMA
- 2.6. Memory
- 2.7. Boot Sequence
- 2.8. Bootrom
- 2.9. Power Supplies
- 2.10. Core Supply Regulator
- 2.11. Power Control
- 2.12. Chip-Level Reset
- 2.13. Power-On State Machine
- 2.14. Subsystem Resets
- 2.15. Clocks
- 2.16. Crystal Oscillator (XOSC)
- 2.17. Ring Oscillator (ROSC)
- 2.18. PLL
- 2.19. GPIO
- 2.20. Sysinfo
- 2.21. Syscfg
- 2.22. TBMAN
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. UART
- 4.3. I2C
- 4.3.1. Features
- 4.3.2. IP Configuration
- 4.3.3. I2C Overview
- 4.3.4. I2C Terminology
- 4.3.5. I2C Behaviour
- 4.3.6. I2C Protocols
- 4.3.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.3.8. Multiple Master Arbitration
- 4.3.9. Clock Synchronization
- 4.3.10. Operation Modes
- 4.3.11. Spike Suppression
- 4.3.12. Fast Mode Plus Operation
- 4.3.13. Bus Clear Feature
- 4.3.14. IC_CLK Frequency Configuration
- 4.3.15. DMA Controller Interface
- 4.3.16. Operation of Interrupt Registers
- 4.3.17. List of Registers
- 4.4. SPI
- 4.5. PWM
- 4.6. Timer
- 4.7. Watchdog
- 4.8. RTC
- 4.9. ADC and Temperature Sensor
- 4.10. SSI
- 4.10.1. Overview
- 4.10.2. Features
- 4.10.3. IP Modifications
- 4.10.4. Clock Ratios
- 4.10.5. Transmit and Receive FIFO Buffers
- 4.10.6. 32-Bit Frame Size Support
- 4.10.7. SSI Interrupts
- 4.10.8. Transfer Modes
- 4.10.9. Operation Modes
- 4.10.10. Partner Connection Interfaces
- 4.10.11. DMA Controller Interface
- 4.10.12. APB Interface
- 4.10.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
- Appendix C: Documentation Release History
Bits Name Description Type Reset
6 HAS_DMA DMA handshaking signals are enabled RO 0x0
5 INTR_IO COMBINED Interrupt outputs RO 0x0
4 HC_COUNT_VALU
ES
Programmable count values for each mode. RO 0x0
3:2 MAX_SPEED_MO
DE
MAX SPEED MODE = FAST MODE RO 0x0
1:0 APB_DATA_WIDT
H
APB data bus width is 32 bits RO 0x0
I2C: IC_COMP_VERSION Register
Offset: 0xf8
Description
I2C Component Version Register
Table 503.
IC_COMP_VERSION
Register
Bits Name Description Type Reset
31:0 IC_COMP_VERSION RO 0x3230312a
I2C: IC_COMP_TYPE Register
Offset: 0xfc
Description
I2C Component Type Register
Table 504.
IC_COMP_TYPE
Register
Bits Name Description Type Reset
31:0 IC_COMP_TYPE Designware Component Type number = 0x44_57_01_40.
This assigned unique hex value is constant and is derived
from the two ASCII letters 'DW' followed by a 16-bit
unsigned number.
RO 0x44570140
4.4. SPI
ARM Documentation
Excerpted from the ARM PrimeCell Synchronous Serial Port (PL022) Technical Reference Manual. Used
with permission.
RP2040 has two identical SPI controllers, both based on an ARM Primecell Synchronous Serial Port (SSP) (PL022)
(Revision r1p4). Note this is NOT the same as the QSPI interface covered in Section 4.10.
Each controller supports the following features:
•
Master or Slave modes
◦
Motorola SPI-compatible interface
◦
Texas Instruments synchronous serial interface
◦
National Semiconductor Microwire interface
RP2040 Datasheet
4.4. SPI 522