Datasheet

PRESETn
PSEL
PENABLE
PWRITE
PADDR[11:2]
PWDATA[15:0]
PRDATA[15:0]
PCLK
AMBA
APB
interface
FIFO status
and interrupt
generation
Transmit and
receive logic
PWDATAIn[15:0] SSPTXINTR
TxRdDataIn[15:0]
SSPRXINTR
SSPRORINTR
SSPRTINTR
PCLK
SSPTXINTR
SSPRXDMACLR
SSPTXDMACLR
SSPRXDMASREQ
SSPRXDMABREQ
SSPTXDMASREQ
SSPTXDMABREQ
RxFRdData
[15:0]
nSSPRST
PCLK
SSPCLKDIV
RxWrData[15:0]
Prescale value
Tx/Rx FIFO watermark levels
Tx/Rx params
SSPCLK
nSSPOE
SSPTXD
SSPFSSOUT
SSPCLKOUT
nSSPCTLOE
SSPCLKIN
SSPFSSIN
SSPRXD
SSPRTRINTR
SSPRORINTR
SSPRXRINTR
SSPINTR
PCLK
PCLK
Tx FIFO
16 bits wide,
8 locations
deep
Rx FIFO
16 bits wide,
8 locations
deep
Clock
prescaler
Register
block
DMA
interface
SSPCLK
SSPCLK
DATAOUTDATAIN
Figure 87. PrimeCell
SSP block diagram.
For clarity, does not
show the test logic.
4.4.2.1. AMBA APB interface
The AMBA APB interface generates read and write decodes for accesses to status and control registers, and transmit
and receive FIFO memories.
4.4.2.2. Register block
The register block stores data written, or to be read, across the AMBA APB interface.
4.4.2.3. Clock prescaler
When configured as a master, an internal prescaler, comprising two free-running reloadable serially linked counters,
provides the serial output clock SSPCLKOUT.
You can program the clock prescaler, using the SSPCPSR register, to divide SSPCLK by a factor of 2-254 in steps of two.
By not utilizing the least significant bit of the SSPCPSR register, division by an odd number is not possible which
ensures that a symmetrical, equal mark space ratio, clock is generated. See SSPCPSR.
The output of the prescaler is divided again by a factor of 1-256, by programming the SSPCR0 control register, to give
the final master output clock SSPCLKOUT.

NOTE
The PCLK and SSPCLK clock inputs in Figure 87 are connected to the clk_sys and clk_peri system-level clock nets on
RP2040, respectively. By default clk_peri is attached directly to the system clock, but can be detached to maintain
constant SPI frequency if the system clock is varied dynamically. See Figure 28 for an overview of the RP2040 clock
architecture.
4.4.2.4. Transmit FIFO
The common transmit FIFO is a 16-bit wide, 8-locations deep memory buffer. CPU data written across the AMBA APB
interface are stored in the buffer until read out by the transmit logic.
RP2040 Datasheet
4.4. SPI 524