Datasheet

When configured as a master or a slave, parallel data is written into the transmit FIFO prior to serial conversion, and
transmission to the attached slave or master respectively, through the SSPTXD pin.
4.4.2.5. Receive FIFO
The common receive FIFO is a 16-bit wide, 8-locations deep memory buffer. Received data from the serial interface are
stored in the buffer until read out by the CPU across the AMBA APB interface.
When configured as a master or slave, serial data received through the SSPRXD pin is registered prior to parallel loading
into the attached slave or master receive FIFO respectively.
4.4.2.6. Transmit and receive logic
When configured as a master, the clock to the attached slaves is derived from a divided-down version of SSPCLK
through the previously described prescaler operations. The master transmit logic successively reads a value from its
transmit FIFO and performs parallel to serial conversion on it. Then, the serial data stream and frame control signal,
synchronized to SSPCLKOUT, are output through the SSPTXD pin to the attached slaves. The master receive logic
performs serial to parallel conversion on the incoming synchronous SSPRXD data stream, extracting and storing values
into its receive FIFO, for subsequent reading through the APB interface.
When configured as a slave, the SSPCLKIN clock is provided by an attached master and used to time its transmission
and reception sequences. The slave transmit logic, under control of the master clock, successively reads a value from
its transmit FIFO, performs parallel to serial conversion, then outputs the serial data stream and frame control signal
through the slave SSPTXD pin. The slave receive logic performs serial to parallel conversion on the incoming SSPRXD
data stream, extracting and storing values into its receive FIFO, for subsequent reading through the APB interface.
4.4.2.7. Interrupt generation logic
The PrimeCell SSP generates four individual maskable, active-HIGH interrupts. A combined interrupt output is generated
as an OR function of the individual interrupt requests.
The transmit and receive dynamic data-flow interrupts, SSPTXINTR and SSPRXINTR, are separated from the status
interrupts so that data can be read or written in response to the FIFO trigger levels.
4.4.2.8. DMA interface
The PrimeCell SSP provides an interface to connect to a DMA controller, see Section 4.4.3.16.
4.4.2.9. Synchronizing registers and logic
The PrimeCell SSP supports both asynchronous and synchronous operation of the clocks, PCLK and SSPCLK.
Synchronization registers and handshaking logic have been implemented, and are active at all times. Synchronization of
control signals is performed on both directions of data flow, that is:
•
from the PCLK to the SSPCLK domain
•
from the SSPCLK to the PCLK domain.
4.4.3. Operation
4.4.3.1. Interface reset
The PrimeCell SSP is reset by the global reset signal, PRESETn, and a block-specific reset signal, nSSPRST. The device
reset controller asserts nSSPRST asynchronously and negate it synchronously to SSPCLK.
RP2040 Datasheet
4.4. SPI 525