Datasheet

4.4.3.2. Configuring the SSP
Following reset, the PrimeCell SSP logic is disabled and must be configured when in this state. It is necessary to
program control registers SSPCR0 and SSPCR1 to configure the peripheral as a master or slave operating under one of
the following protocols:
•
Motorola SPI
•
Texas Instruments SSI
•
National Semiconductor.
The bit rate, derived from the external SSPCLK, requires the programming of the clock prescale register SSPCPSR.
4.4.3.3. Enable PrimeCell SSP operation
You can either prime the transmit FIFO, by writing up to eight 16-bit values when the PrimeCell SSP is disabled, or permit
the transmit FIFO service request to interrupt the CPU. Once enabled, transmission or reception of data begins on the
transmit, SSPTXD, and receive, SSPRXD, pins.
4.4.3.4. Clock ratios
There is a constraint on the ratio of the frequencies of PCLK to SSPCLK. The frequency of SSPCLK must be less than or
equal to that of PCLK. This ensures that control signals from the SSPCLK domain to the PCLK domain are guaranteed
to get synchronized before one frame duration:
.
In the slave mode of operation, the SSPCLKIN signal from the external master is double-synchronized and then delayed
to detect an edge. It takes three SSPCLKs to detect an edge on SSPCLKIN. SSPTXD has less setup time to the falling
edge of SSPCLKIN on which the master is sampling the line.
The setup and hold times on SSPRXD, with reference to SSPCLKIN, must be more conservative to ensure that it is at the
right value when the actual sampling occurs within the SSPMS. To ensure correct device operation, SSPCLK must be at
least 12 times faster than the maximum expected frequency of SSPCLKIN.
The frequency selected for SSPCLK must accommodate the desired range of bit clock rates. The ratio of minimum
SSPCLK frequency to SSPCLKOUT maximum frequency in the case of the slave mode is 12, and for the master mode, it
is two.
To generate a maximum bit rate of 1.8432Mbps in the master mode, the frequency of SSPCLK must be at least
3.6864MHz. With an SSPCLK frequency of 3.6864MHz, the SSPCPSR register must be programmed with a value of 2,
and the SCR[7:0] field in the SSPCR0 register must be programmed with a value of 0.
To work with a maximum bit rate of 1.8432Mbps in the slave mode, the frequency of SSPCLK must be at least
22.12MHz. With an SSPCLK frequency of 22.12MHz, the SSPCPSR register can be programmed with a value of 12, and
the SCR[7:0] field in the SSPCR0 register can be programmed with a value of 0. Similarly, the ratio of SSPCLK maximum
frequency to SSPCLKOUT minimum frequency is 254 x 256.
The minimum frequency of SSPCLK is governed by the following equations, both of which must be satisfied:
, for master mode
, for slave mode.
The maximum frequency of SSPCLK is governed by the following equations, both of which must be satisfied:
, for master mode
, for slave mode.
RP2040 Datasheet
4.4. SPI 526