Datasheet

Table 45.
DIV_REMAINDER
Register
Bits Description Type Reset
31:0 Divider result remainder
The result of DIVIDEND % DIVISOR (modulo). Contents undefined while
CSR_READY is low.
For signed calculations, REMAINDER is negative only when DIVIDEND is
negative.
This register can be written to directly, for context save/restore purposes. This
halts any
in-progress calculation and sets the CSR_READY and CSR_DIRTY flags.
RW 0x00000000
SIO: DIV_CSR Register
Offset: 0x078
Description
Control and status register for divider.
Table 46. DIV_CSR
Register
Bits Name Description Type Reset
31:2 Reserved. - - -
1 DIRTY Changes to 1 when any register is written, and back to 0
when QUOTIENT is read.
Software can use this flag to make save/restore more
efficient (skip if not DIRTY).
If the flag is used in this way, it’s recommended to either
read QUOTIENT only,
or REMAINDER and then QUOTIENT, to prevent data loss
on context switch.
RO 0x0
0 READY Reads as 0 when a calculation is in progress, 1 otherwise.
Writing an operand (xDIVIDEND, xDIVISOR) will
immediately start a new calculation, no
matter if one is already in progress.
Writing to a result register will immediately terminate any
in-progress calculation
and set the READY and DIRTY flags.
RO 0x1
SIO: INTERP0_ACCUM0 Register
Offset: 0x080
Table 47.
INTERP0_ACCUM0
Register
Bits Description Type Reset
31:0 Read/write access to accumulator 0 RW 0x00000000
SIO: INTERP0_ACCUM1 Register
Offset: 0x084
Table 48.
INTERP0_ACCUM1
Register
Bits Description Type Reset
31:0 Read/write access to accumulator 1 RW 0x00000000
SIO: INTERP0_BASE0 Register
Offset: 0x088
RP2040 Datasheet
2.3. Processor subsystem 52