Datasheet

However, in the case of continuous back-to-back transmissions, the SSPFSSOUT signal must be pulsed HIGH between
each data word transfer. This is because the slave select pin freezes the data in its serial peripheral register and does
not permit it to be altered if the SPH bit is logic zero. Therefore, the master device must raise the SSPFSSIN pin of the
slave device between each data transfer to enable the serial peripheral data write. On completion of the continuous
transfer, the SSPFSSOUT pin is returned to its idle state one SSPCLKOUT period after the last bit has been captured.
4.4.3.13. Motorola SPI Format with SPO=1, SPH=1
Figure 95 shows the transfer signal sequence for Motorola SPI format with SPO=1, SPH=1, and it covers both single and
continuous transfers.
SSPCLKOUT/SSPCLIN
SSPFSSOUT/SSPFSSIN
SSPRXD
MSB LSBQ Q
SSPRXD
MSB LSB
4 to 16 bits
nSSPOE
Figure 95. Motorola
SPI frame format with
SPO=1 and SPH=1,
single and continuous
transfers

NOTE
In Figure 95, Q is an undefined signal.
In this configuration, during idle periods:
•
the SSPCLKOUT signal is forced HIGH
•
the SSPFSSOUT signal is forced HIGH
•
the transmit data line SSPTXD is arbitrarily forced LOW
•
the nSSPOE pad enable signal is forced HIGH, making the transmit pad high impedance
•
when the PrimeCell SSP is configured as a master, the nSSPCTLOE line is driven LOW, enabling the SSPCLKOUT
pad, active-LOW enable
•
when the PrimeCell SSP is configured as a slave, the nSSPCTLOE line is driven HIGH, disabling the SSPCLKOUT
pad, active-LOW enable.
If the PrimeCell SSP is enabled, and there is valid data within the transmit FIFO, the start of transmission is signified by
the SSPFSSOUT master signal being driven LOW. The nSSPOE line is driven LOW, enabling the master SSPTXD output
pad. After an additional one half SSPCLKOUT period, both master and slave data are enabled onto their respective
transmission lines. At the same time, the SSPCLKOUT is enabled with a falling edge transition. Data is then captured on
the rising edges and propagated on the falling edges of the SSPCLKOUT signal.
After all bits have been transferred, in the case of a single word transmission, the SSPFSSOUT line is returned to its idle
HIGH state one SSPCLKOUT period after the last bit has been captured.
For continuous back-to-back transmissions, the SSPFSSOUT pin remains in its active-LOW state, until the final bit of the
last word has been captured, and then returns to its idle state as the previous section describes.
For continuous back-to-back transfers, the SSPFSSOUT pin is held LOW between successive data words and
termination is the same as that of the single word transfer.
4.4.3.14. National Semiconductor Microwire frame format
Figure 96 shows the National Semiconductor Microwire frame format for a single frame. Figure 97 shows the same
format when back to back frames are transmitted.
RP2040 Datasheet
4.4. SPI 532