Datasheet

SSPCLKOUT/SSPCLIN
SSPFSSOUT/SSPFSSIN
SSPTXD
SSPRXD
nSSPOE
MSB LSB
MSB0 LSB
8-bit control
4 to 16 bits output data
Figure 96. Microwire
frame format, single
transfer
Microwire format is very similar to SPI format, except that transmission is half-duplex instead of full-duplex, using a
master-slave message passing technique. Each serial transmission begins with an 8-bit control word that is transmitted
from the PrimeCell SSP to the off-chip slave device. During this transmission, the PrimeCell SSP receives no incoming
data. After the message has been sent, the off-chip slave decodes it and, after waiting one serial clock after the last bit
of the 8-bit control message has been sent, responds with the required data. The returned data is 4 to 16 bits in length,
making the total frame length in the range 13-25 bits.
In this configuration, during idle periods:
•
SSPCLKOUT is forced LOW
•
SSPFSSOUT is forced HIGH
•
the transmit data line, SSPTXD, is arbitrarily forced LOW
•
the nSSPOE pad enable signal is forced HIGH, making the transmit pad high impedance.
A transmission is triggered by writing a control byte to the transmit FIFO. The falling edge of SSPFSSOUT causes the
value contained in the bottom entry of the transmit FIFO to be transferred to the serial shift register of the transmit logic,
and the MSB of the 8-bit control frame to be shifted out onto the SSPTXD pin. SSPFSSOUT remains LOW for the
duration of the frame transmission. The SSPRXD pin remains tristated during this transmission.
The off-chip serial slave device latches each control bit into its serial shifter on the rising edge of each SSPCLKOUT.
After the last bit is latched by the slave device, the control byte is decoded during a one clock wait-state, and the slave
responds by transmitting data back to the PrimeCell SSP. Each bit is driven onto SSPRXD line on the falling edge of
SSPCLKOUT. The PrimeCell SSP in turn latches each bit on the rising edge of SSPCLKOUT. At the end of the frame, for
single transfers, the SSPFSSOUT signal is pulled HIGH one clock period after the last bit has been latched in the receive
serial shifter, that causes the data to be transferred to the receive FIFO.

NOTE
The off-chip slave device can tristate the receive line either on the falling edge of SSPCLKOUT after the LSB has
been latched by the receive shifter, or when the SSPFSSOUT pin goes HIGH.
For continuous transfers, data transmission begins and ends in the same manner as a single transfer. However, the
SSPFSSOUT line is continuously asserted, held LOW, and transmission of data occurs back-to-back. The control byte of
the next frame follows directly after the LSB of the received data from the current frame. Each of the received values is
transferred from the receive shifter on the falling edge SSPCLKOUT, after the LSB of the frame has been latched into the
PrimeCell SSP.
Figure 97 shows the National Semiconductor Microwire frame format when back-to-back frames are transmitted.
SSPCLKOUT/SSPCLIN
SSPFSSOUT/SSPFSSIN
SSPTXD
SSPRXD
nSSPOE
MSB LSBLSB
MSB0 MSBLSB
8-bit control
4 to 16 bits output data
Figure 97. Microwire
frame format,
continuous transfers
In Microwire mode, the PrimeCell SSP slave samples the first bit of receive data on the rising edge of SSPCLKIN after
SSPFSSIN has gone LOW. Masters that drive a free-running SSPCKLIN must ensure that the SSPFSSIN signal has
sufficient setup and hold margins with respect to the rising edge of SSPCLKIN.
Figure 98 shows these setup and hold time requirements.
RP2040 Datasheet
4.4. SPI 533