Datasheet

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Table Of Contents

SSPTXDMASREQ

Single-character DMA transfer request, asserted by the SSP. This signal is asserted when there is at least one

empty location in the transmit FIFO.

SSPTXDMABREQ

Burst DMA transfer request, asserted by the SSP. This signal is asserted when the transmit FIFO contains four

characters or fewer.

SSPTXDMACLR

DMA request clear, asserted by the DMA controller, to clear the transmit request signals. If a DMA burst transfer is

requested, the clear signal is asserted during the transfer of the last data in the burst.

The burst transfer and single transfer request signals are not mutually exclusive. They can both be asserted at the same

time. For example, when there is more data than the watermark level of four in the receive FIFO, the burst transfer

request, and the single transfer request, are asserted. When the amount of data left in the receive FIFO is less than the

watermark level, the single request only is asserted. This is useful for situations where the number of characters left to

be received in the stream is less than a burst.

For example, if 19 characters must be received, the DMA controller then transfers four bursts of four characters, and

three single transfers to complete the stream.



NOTE

For the remaining three characters, the PrimeCell SSP does not assert the burst request.

Each request signal remains asserted until the relevant DMA clear signal is asserted. After the request clear signal is

deasserted, a request signal can become active again, depending on the conditions that previous sections describe. All

request signals are deasserted if the PrimeCell SSP is disabled, or the DMA enable signal is cleared.

Table 505 shows the trigger points for DMABREQ, for both the transmit and receive FIFOs.

Table 505. DMA

trigger points for the

transmit and receive

FIFOs

Burst length

Watermark level Transmit, number of empty locations Receive, number of filled locations

1/2 4 4

Figure 102 shows the timing diagram for both a single transfer request, and a burst transfer request, with the

appropriate DMA clear signal. The signals are all synchronous to PCLK.

PCLK

DMABREQ

DMASREQ

DMACLR

Figure 102. DMA

transfer waveforms

4.4.4. List of Registers

The SPI0 and SPI1 registers start at base addresses of 0x4003c000 and 0x40040000 respectively (defined as SPI0_BASE