Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.5. DMA
- 2.6. Memory
- 2.7. Boot Sequence
- 2.8. Bootrom
- 2.9. Power Supplies
- 2.10. Core Supply Regulator
- 2.11. Power Control
- 2.12. Chip-Level Reset
- 2.13. Power-On State Machine
- 2.14. Subsystem Resets
- 2.15. Clocks
- 2.16. Crystal Oscillator (XOSC)
- 2.17. Ring Oscillator (ROSC)
- 2.18. PLL
- 2.19. GPIO
- 2.20. Sysinfo
- 2.21. Syscfg
- 2.22. TBMAN
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. UART
- 4.3. I2C
- 4.3.1. Features
- 4.3.2. IP Configuration
- 4.3.3. I2C Overview
- 4.3.4. I2C Terminology
- 4.3.5. I2C Behaviour
- 4.3.6. I2C Protocols
- 4.3.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.3.8. Multiple Master Arbitration
- 4.3.9. Clock Synchronization
- 4.3.10. Operation Modes
- 4.3.11. Spike Suppression
- 4.3.12. Fast Mode Plus Operation
- 4.3.13. Bus Clear Feature
- 4.3.14. IC_CLK Frequency Configuration
- 4.3.15. DMA Controller Interface
- 4.3.16. Operation of Interrupt Registers
- 4.3.17. List of Registers
- 4.4. SPI
- 4.5. PWM
- 4.6. Timer
- 4.7. Watchdog
- 4.8. RTC
- 4.9. ADC and Temperature Sensor
- 4.10. SSI
- 4.10.1. Overview
- 4.10.2. Features
- 4.10.3. IP Modifications
- 4.10.4. Clock Ratios
- 4.10.5. Transmit and Receive FIFO Buffers
- 4.10.6. 32-Bit Frame Size Support
- 4.10.7. SSI Interrupts
- 4.10.8. Transfer Modes
- 4.10.9. Operation Modes
- 4.10.10. Partner Connection Interfaces
- 4.10.11. DMA Controller Interface
- 4.10.12. APB Interface
- 4.10.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
- Appendix C: Documentation Release History
Offset Name Info
0x014 SSPIMSC Interrupt mask set or clear register, SSPIMSC on page 3-9
0x018 SSPRIS Raw interrupt status register, SSPRIS on page 3-10
0x01c SSPMIS Masked interrupt status register, SSPMIS on page 3-11
0x020 SSPICR Interrupt clear register, SSPICR on page 3-11
0x024 SSPDMACR DMA control register, SSPDMACR on page 3-12
0xfe0 SSPPERIPHID0 Peripheral identification registers, SSPPeriphID0-3 on page 3-13
0xfe4 SSPPERIPHID1 Peripheral identification registers, SSPPeriphID0-3 on page 3-13
0xfe8 SSPPERIPHID2 Peripheral identification registers, SSPPeriphID0-3 on page 3-13
0xfec SSPPERIPHID3 Peripheral identification registers, SSPPeriphID0-3 on page 3-13
0xff0 SSPPCELLID0 PrimeCell identification registers, SSPPCellID0-3 on page 3-16
0xff4 SSPPCELLID1 PrimeCell identification registers, SSPPCellID0-3 on page 3-16
0xff8 SSPPCELLID2 PrimeCell identification registers, SSPPCellID0-3 on page 3-16
0xffc SSPPCELLID3 PrimeCell identification registers, SSPPCellID0-3 on page 3-16
SPI: SSPCR0 Register
Offset: 0x000
Description
Control register 0, SSPCR0 on page 3-4
Table 507. SSPCR0
Register
Bits Name Description Type Reset
31:16 Reserved. - - -
15:8 SCR Serial clock rate. The value SCR is used to generate the
transmit and receive bit rate of the PrimeCell SSP. The bit
rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is
an even value from 2-254, programmed through the
SSPCPSR register and SCR is a value from 0-255.
RW 0x00
7 SPH SSPCLKOUT phase, applicable to Motorola SPI frame
format only. See Motorola SPI frame format on page 2-10.
RW 0x0
6 SPO SSPCLKOUT polarity, applicable to Motorola SPI frame
format only. See Motorola SPI frame format on page 2-10.
RW 0x0
5:4 FRF Frame format: 00 Motorola SPI frame format. 01 TI
synchronous serial frame format. 10 National Microwire
frame format. 11 Reserved, undefined operation.
RW 0x0
3:0 DSS Data Size Select: 0000 Reserved, undefined operation.
0001 Reserved, undefined operation. 0010 Reserved,
undefined operation. 0011 4-bit data. 0100 5-bit data.
0101 6-bit data. 0110 7-bit data. 0111 8-bit data. 1000 9-
bit data. 1001 10-bit data. 1010 11-bit data. 1011 12-bit
data. 1100 13-bit data. 1101 14-bit data. 1110 15-bit data.
1111 16-bit data.
RW 0x0
SPI: SSPCR1 Register
Offset: 0x004
RP2040 Datasheet
4.4. SPI 537