Datasheet

Description
Control register 1, SSPCR1 on page 3-5
Table 508. SSPCR1
Register
Bits Name Description Type Reset
31:4 Reserved. - - -
3 SOD Slave-mode output disable. This bit is relevant only in the
slave mode, MS=1. In multiple-slave systems, it is possible
for an PrimeCell SSP master to broadcast a message to
all slaves in the system while ensuring that only one slave
drives data onto its serial output line. In such systems the
RXD lines from multiple slaves could be tied together. To
operate in such systems, the SOD bit can be set if the
PrimeCell SSP slave is not supposed to drive the SSPTXD
line: 0 SSP can drive the SSPTXD output in slave mode. 1
SSP must not drive the SSPTXD output in slave mode.
RW 0x0
2 MS Master or slave mode select. This bit can be modified only
when the PrimeCell SSP is disabled, SSE=0: 0 Device
configured as master, default. 1 Device configured as
slave.
RW 0x0
1 SSE Synchronous serial port enable: 0 SSP operation disabled.
1 SSP operation enabled.
RW 0x0
0 LBM Loop back mode: 0 Normal serial port operation enabled.
1 Output of transmit serial shifter is connected to input of
receive serial shifter internally.
RW 0x0
SPI: SSPDR Register
Offset: 0x008
Description
Data register, SSPDR on page 3-6
Table 509. SSPDR
Register
Bits Name Description Type Reset
31:16 Reserved. - - -
15:0 DATA Transmit/Receive FIFO: Read Receive FIFO. Write
Transmit FIFO. You must right-justify data when the
PrimeCell SSP is programmed for a data size that is less
than 16 bits. Unused bits at the top are ignored by
transmit logic. The receive logic automatically right-
justifies.
RWF -
SPI: SSPSR Register
Offset: 0x00c
Description
Status register, SSPSR on page 3-7
Table 510. SSPSR
Register
Bits Name Description Type Reset
31:5 Reserved. - - -
RP2040 Datasheet
4.4. SPI 538