Datasheet

Bits Name Description Type Reset
4 BSY PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is
currently transmitting and/or receiving a frame or the
transmit FIFO is not empty.
RO 0x0
3 RFF Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive
FIFO is full.
RO 0x0
2 RNE Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1
Receive FIFO is not empty.
RO 0x0
1 TNF Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1
Transmit FIFO is not full.
RO 0x1
0 TFE Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1
Transmit FIFO is empty.
RO 0x1
SPI: SSPCPSR Register
Offset: 0x010
Description
Clock prescale register, SSPCPSR on page 3-8
Table 511. SSPCPSR
Register
Bits Name Description Type Reset
31:8 Reserved. - - -
7:0 CPSDVSR Clock prescale divisor. Must be an even number from 2-
254, depending on the frequency of SSPCLK. The least
significant bit always returns zero on reads.
RW 0x00
SPI: SSPIMSC Register
Offset: 0x014
Description
Interrupt mask set or clear register, SSPIMSC on page 3-9
Table 512. SSPIMSC
Register
Bits Name Description Type Reset
31:4 Reserved. - - -
3 TXIM Transmit FIFO interrupt mask: 0 Transmit FIFO half empty
or less condition interrupt is masked. 1 Transmit FIFO half
empty or less condition interrupt is not masked.
RW 0x0
2 RXIM Receive FIFO interrupt mask: 0 Receive FIFO half full or
less condition interrupt is masked. 1 Receive FIFO half full
or less condition interrupt is not masked.
RW 0x0
1 RTIM Receive timeout interrupt mask: 0 Receive FIFO not empty
and no read prior to timeout period interrupt is masked. 1
Receive FIFO not empty and no read prior to timeout
period interrupt is not masked.
RW 0x0
0 RORIM Receive overrun interrupt mask: 0 Receive FIFO written to
while full condition interrupt is masked. 1 Receive FIFO
written to while full condition interrupt is not masked.
RW 0x0
SPI: SSPRIS Register
RP2040 Datasheet
4.4. SPI 539