Datasheet

A
B
Count
0 1 2 3 0 1 2 3 0 1 2 3
Figure 105. The slice
counts repeatedly
from 0 to 3, which is
configured as the TOP
value. The output
waves therefore have
a period of 4. Output A
is high for 1 cycle in 4,
so the average output
voltage is 1/4 of the
IO supply voltage.
Output B is high for 3
cycles in every 4. Note
the rising edges of A
and B are always
aligned.
The default behaviour of a PWM slice is to count upward until the value of the TOP register is reached, and then
immediately wrap to 0. PWM slices also offer a phase-correct mode, enabled by setting CSR_PH_CORRECT to 1, where the
counter starts to count downward after reaching TOP, until it reaches 0 again.
It is called phase-correct mode because the pulse is always centred on the same point, no matter the duty cycle. In
other words, its phase is not a function of duty cycle. The output frequency is halved when phase-correct mode is
enabled.
TOP
Count
IOVDD
TOP/3
V
Input (Count)
Counter compare level
Counter
0
T 2T 3T
t
Output (Pulse)
GPIO pulse output
0
T 2T 3T
t
Figure 106. In phase-
correct mode, the
counter counts back
down from TOP to 0
once it reaches TOP.
4.5.2.2. 0% and 100% Duty Cycle
The RP2040 PWM can produce toggle-free 0% and 100% duty cycle output.
TOP
Input (Count)
Count
Counter compare level
Counter
0
T 2T 3T
t
IOVDD
Output (Pulse)
V
GPIO pulse output
0
T 2T 3T
t
Figure 107. Glitch-free
0% duty cycle output
for CC = 0, and glitch-
free 100% duty cycle
output for CC = TOP +
1
A CC value of 0 will produce a 0% output, i.e. the output signal is always low. A CC value of TOP + 1 (i.e. equal to the period,
in non-phase-correct mode) will produce a 100% output. For example, if TOP is programmed to 254, the counter will have
a period of 255 cycles, and CC values in the range of 0 to 255 inclusive will produce duty cycles in the range 0% to 100%
inclusive.
Glitch-free output at 0% and 100% is important e.g. to avoid switching losses when a MOSFET is controlled at its
minimum and maximum current levels.
RP2040 Datasheet
4.5. PWM 545