Datasheet

Table 56.
INTERP0_PEEK_LANE
1 Register
Bits Description Type Reset
31:0 Read LANE1 result, without altering any internal state (PEEK). RO 0x00000000
SIO: INTERP0_PEEK_FULL Register
Offset: 0x0a8
Table 57.
INTERP0_PEEK_FULL
Register
Bits Description Type Reset
31:0 Read FULL result, without altering any internal state (PEEK). RO 0x00000000
SIO: INTERP0_CTRL_LANE0 Register
Offset: 0x0ac
Description
Control register for lane 0
Table 58.
INTERP0_CTRL_LANE
0 Register
Bits Name Description Type Reset
31:26 Reserved. - - -
25 OVERF Set if either OVERF0 or OVERF1 is set. RO 0x0
24 OVERF1 Indicates if any masked-off MSBs in ACCUM1 are set. RO 0x0
23 OVERF0 Indicates if any masked-off MSBs in ACCUM0 are set. RO 0x0
22 Reserved. - - -
21 BLEND Only present on INTERP0 on each core. If BLEND mode is
enabled:
- LANE1 result is a linear interpolation between BASE0 and
BASE1, controlled
by the 8 LSBs of lane 1 shift and mask value (a fractional
number between
0 and 255/256ths)
- LANE0 result does not have BASE0 added (yields only
the 8 LSBs of lane 1 shift+mask value)
- FULL result does not have lane 1 shift+mask value added
(BASE2 + lane 0 shift+mask)
LANE1 SIGNED flag controls whether the interpolation is
signed or unsigned.
RW 0x0
20:19 FORCE_MSB ORed into bits 29:28 of the lane result presented to the
processor on the bus.
No effect on the internal 32-bit datapath. Handy for using
a lane to generate sequence
of pointers into flash or SRAM.
RW 0x0
18 ADD_RAW If 1, mask + shift is bypassed for LANE0 result. This does
not affect FULL result.
RW 0x0
17 CROSS_RESULT If 1, feed the opposite lane’s result into this lane’s
accumulator on POP.
RW 0x0
16 CROSS_INPUT If 1, feed the opposite lane’s accumulator into this lane’s
shift + mask hardware.
Takes effect even if ADD_RAW is set (the CROSS_INPUT
mux is before the shift+mask bypass)
RW 0x0
RP2040 Datasheet
2.3. Processor subsystem 54