Datasheet

Offset Name Info
0xa0 EN This register aliases the CSR_EN bits for all channels.
Writing to this register allows multiple channels to be enabled
or disabled simultaneously, so they can run in perfect sync.
For each channel, there is only one physical EN register bit,
which can be accessed through here or CHx_CSR.
0xa4 INTR Raw Interrupts
0xa8 INTE Interrupt Enable
0xac INTF Interrupt Force
0xb0 INTS Interrupt status after masking & forcing
PWM: CH0_CSR, CH1_CSR, …, CH6_CSR, CH7_CSR Registers
Offsets: 0x00, 0x14, …, 0x78, 0x8c
Description
Control and status register
Table 527. CH0_CSR,
CH1_CSR, …,
CH6_CSR, CH7_CSR
Registers
Bits Name Description Type Reset
31:8 Reserved. - - -
7 PH_ADV Advance the phase of the counter by 1 count, while it is
running.
Self-clearing. Write a 1, and poll until low. Counter must be
running
at less than full speed (div_int + div_frac / 16 > 1)
SC 0x0
6 PH_RET Retard the phase of the counter by 1 count, while it is
running.
Self-clearing. Write a 1, and poll until low. Counter must be
running.
SC 0x0
5:4 DIVMODE
0x0 → Free-running counting at rate dictated by fractional
divider
0x1 → Fractional divider operation is gated by the PWM B
pin.
0x2 → Counter advances with each rising edge of the
PWM B pin.
0x3 → Counter advances with each falling edge of the
PWM B pin.
RW 0x0
3 B_INV Invert output B RW 0x0
2 A_INV Invert output A RW 0x0
1 PH_CORRECT 1: Enable phase-correct modulation. 0: Trailing-edge RW 0x0
0 EN Enable the PWM channel. RW 0x0
PWM: CH0_DIV, CH1_DIV, …, CH6_DIV, CH7_DIV Registers
Offsets: 0x04, 0x18, …, 0x7c, 0x90
Description
INT and FRAC form a fixed-point fractional number.
Counting rate is system clock frequency divided by this number.
Fractional division uses simple 1st-order sigma-delta.
RP2040 Datasheet
4.5. PWM 552