Datasheet

Table 528. CH0_DIV,
CH1_DIV, …, CH6_DIV,
CH7_DIV Registers
Bits Name Description Type Reset
31:12 Reserved. - - -
11:4 INT RW 0x01
3:0 FRAC RW 0x0
PWM: CH0_CTR, CH1_CTR, …, CH6_CTR, CH7_CTR Registers
Offsets: 0x08, 0x1c, …, 0x80, 0x94
Table 529. CH0_CTR,
CH1_CTR, …,
CH6_CTR, CH7_CTR
Registers
Bits Description Type Reset
31:16 Reserved. - -
15:0 Direct access to the PWM counter RW 0x0000
PWM: CH0_CC, CH1_CC, …, CH6_CC, CH7_CC Registers
Offsets: 0x0c, 0x20, …, 0x84, 0x98
Description
Counter compare values
Table 530. CH0_CC,
CH1_CC, …, CH6_CC,
CH7_CC Registers
Bits Name Description Type Reset
31:16 B RW 0x0000
15:0 A RW 0x0000
PWM: CH0_TOP, CH1_TOP, …, CH6_TOP, CH7_TOP Registers
Offsets: 0x10, 0x24, …, 0x88, 0x9c
Table 531. CH0_TOP,
CH1_TOP, …,
CH6_TOP, CH7_TOP
Registers
Bits Description Type Reset
31:16 Reserved. - -
15:0 Counter wrap value RW 0xffff
PWM: EN Register
Offset: 0xa0
Description
This register aliases the CSR_EN bits for all channels.
Writing to this register allows multiple channels to be enabled
or disabled simultaneously, so they can run in perfect sync.
For each channel, there is only one physical EN register bit,
which can be accessed through here or CHx_CSR.
Table 532. EN Register
Bits Name Description Type Reset
31:8 Reserved. - - -
7 CH7 RW 0x0
6 CH6 RW 0x0
5 CH5 RW 0x0
4 CH4 RW 0x0
3 CH3 RW 0x0
RP2040 Datasheet
4.5. PWM 553