Datasheet

Description
Interrupt Force
Table 535. INTF
Register
Bits Name Description Type Reset
31:8 Reserved. - - -
7 CH7 RW 0x0
6 CH6 RW 0x0
5 CH5 RW 0x0
4 CH4 RW 0x0
3 CH3 RW 0x0
2 CH2 RW 0x0
1 CH1 RW 0x0
0 CH0 RW 0x0
PWM: INTS Register
Offset: 0xb0
Description
Interrupt status after masking & forcing
Table 536. INTS
Register
Bits Name Description Type Reset
31:8 Reserved. - - -
7 CH7 RO 0x0
6 CH6 RO 0x0
5 CH5 RO 0x0
4 CH4 RO 0x0
3 CH3 RO 0x0
2 CH2 RO 0x0
1 CH1 RO 0x0
0 CH0 RO 0x0
4.6. Timer
4.6.1. Overview
The system timer peripheral on RP2040 provides a global microsecond timebase for the system, and generates
interrupts based on this timebase. It supports the following features:
•
A single 64-bit counter, incrementing once per microsecond
•
This counter can be read from a pair of latching registers, for race-free reads over a 32-bit bus.
•
Four alarms: match on the lower 32 bits of counter, IRQ on match.
The timer uses a one microsecond reference that is generated in the Watchdog (see Section 4.7.2), and derived from
RP2040 Datasheet
4.6. Timer 555