Datasheet

the reference clock (Figure 28), which itself is usually connected directly to the crystal oscillator (Section 2.16).
The 64-bit counter effectively can not overflow (thousands of years at 1 MHz), so the system timer is completely
monotonic in practice.
4.6.1.1. Other Timer Resources on RP2040
The system timer is intended to provide a global timebase for software. RP2040 has a number of other programmable
counter resources which can provide regular interrupts, or trigger DMA transfers.
•
The PWM (Section 4.5) contains 8× 16-bit programmable counters, which run at up to system speed, can generate
interrupts, and can be continuously reprogrammed via the DMA, or trigger DMA transfers to other peripherals.
•
8× PIO state machines (Chapter 3) can count 32-bit values at system speed, and generate interrupts.
•
The DMA (Section 2.5) has four internal pacing timers, which trigger transfers at regular intervals.
•
Each Cortex-M0+ core (Section 2.4) has a standard 24-bit SysTick timer, counting either the microsecond tick
(Section 4.7.2) or the system clock.
4.6.2. Counter
The timer has a 64-bit counter, but RP2040 only has a 32-bit data bus. This means that the TIME value is accessed
through a pair of registers. These are:
•
TIMEHW and TIMELW to write the time
•
TIMEHR and TIMELR to read the time
These pairs are used by accessing the lower register, L, followed by the higher register, H. In the read case, reading the L
register latches the value in the H register so that an accurate time can be read. Alternatively, TIMERAWH and
TIMERAWL can be used to read the raw time without any latching.

CAUTION
While it is technically possible to force a new time value by writing to the TIMEHW and TIMELW registers,
programmers are discouraged from doing this. This is because the timer value is expected to be monotonically
increasing by the SDK which uses it for timeouts, elapsed time etc.
4.6.3. Alarms
The timer has 4 alarms, and outputs a separate interrupt for each alarm. The alarms match on the lower 32 bits of the
64-bit counter which means they can be fired at a maximum of 2
32
microseconds into the future. This is equivalent to:
•
2
32
÷ 10
6
: ~4295 seconds
•
4295 ÷ 60: ~72 minutes

NOTE
This timer is expected to be used for short sleeps. If you want a longer alarm see Section 4.8.
To enable an alarm:
•
Enable the interrupt at the timer with a write to the appropriate alarm bit in INTE: i.e. (1 << 0) for ALARM0
•
Enable the appropriate timer interrupt at the processor (see Section 2.3.2)
•
Write the time you would like the interrupt to fire to ALARM0 (i.e. the current value in TIMERAWL plus your desired
alarm time in microseconds). Writing the time to the ALARM register sets the ARMED bit as a side effect.
RP2040 Datasheet
4.6. Timer 556