Datasheet

Offset Name Info
0x08 TIMEHR Read from bits 63:32 of time
always read timelr before timehr
0x0c TIMELR Read from bits 31:0 of time
0x10 ALARM0 Arm alarm 0, and configure the time it will fire.
Once armed, the alarm fires when TIMER_ALARM0 == TIMELR.
The alarm will disarm itself once it fires, and can
be disarmed early using the ARMED status register.
0x14 ALARM1 Arm alarm 1, and configure the time it will fire.
Once armed, the alarm fires when TIMER_ALARM1 == TIMELR.
The alarm will disarm itself once it fires, and can
be disarmed early using the ARMED status register.
0x18 ALARM2 Arm alarm 2, and configure the time it will fire.
Once armed, the alarm fires when TIMER_ALARM2 == TIMELR.
The alarm will disarm itself once it fires, and can
be disarmed early using the ARMED status register.
0x1c ALARM3 Arm alarm 3, and configure the time it will fire.
Once armed, the alarm fires when TIMER_ALARM3 == TIMELR.
The alarm will disarm itself once it fires, and can
be disarmed early using the ARMED status register.
0x20 ARMED Indicates the armed/disarmed status of each alarm.
A write to the corresponding ALARMx register arms the alarm.
Alarms automatically disarm upon firing, but writing ones here
will disarm immediately without waiting to fire.
0x24 TIMERAWH Raw read from bits 63:32 of time (no side effects)
0x28 TIMERAWL Raw read from bits 31:0 of time (no side effects)
0x2c DBGPAUSE Set bits high to enable pause when the corresponding debug
ports are active
0x30 PAUSE Set high to pause the timer
0x34 INTR Raw Interrupts
0x38 INTE Interrupt Enable
0x3c INTF Interrupt Force
0x40 INTS Interrupt status after masking & forcing
TIMER: TIMEHW Register
Offset: 0x00
Table 538. TIMEHW
Register
Bits Description Type Reset
31:0 Write to bits 63:32 of time
always write timelw before timehw
WF 0x00000000
TIMER: TIMELW Register
Offset: 0x04
RP2040 Datasheet
4.6. Timer 561