Datasheet


WARNING
Due to a logic error, the watchdog counter is decremented twice per tick. Which means the programmer needs to
program double the intended count down value. The SDK examples take this issue into account. See RP2040-E1 for
more information.
4.7.4. Scratch Registers
The watchdog contains eight 32-bit scratch registers that can be used to store information between soft resets of the
chip. A rst_n_run event triggered by toggling the RUN pin or cycling the digital core supply (DVDD) will reset the scratch
registers.
The bootrom checks the watchdog scratch registers for a magic number on boot. This can be used to soft reset the
chip into some user specified code. See Section 2.8.1.1 for more information.
4.7.5. Programmer’s Model
The SDK provides a hardware_watchdog driver to control the watchdog.
4.7.5.1. Enabling the watchdog
SDK: https://github.com/raspberrypi/pico-sdk/tree/master/src/rp2_common/hardware_watchdog/watchdog.c Lines 35 - 64
35 // Helper function used by both watchdog_enable and watchdog_reboot
36 void _watchdog_enable(uint32_t delay_ms, bool pause_on_debug) {
37 hw_clear_bits(&watchdog_hw->ctrl, WATCHDOG_CTRL_ENABLE_BITS);
38
39 // Reset everything apart from ROSC and XOSC
40 hw_set_bits(&psm_hw->wdsel, PSM_WDSEL_BITS & ~(PSM_WDSEL_ROSC_BITS |
Ê PSM_WDSEL_XOSC_BITS));
41
42 uint32_t dbg_bits = WATCHDOG_CTRL_PAUSE_DBG0_BITS |
43 WATCHDOG_CTRL_PAUSE_DBG1_BITS |
44 WATCHDOG_CTRL_PAUSE_JTAG_BITS;
45
46 if (pause_on_debug) {
47 hw_set_bits(&watchdog_hw->ctrl, dbg_bits);
48 } else {
49 hw_clear_bits(&watchdog_hw->ctrl, dbg_bits);
50 }
51
52 if (!delay_ms) delay_ms = 50;
53
54 // Note, we have x2 here as the watchdog HW currently decrements twice per tick
55 load_value = delay_ms * 1000 * 2;
56
57 if (load_value > 0xffffffu)
58 load_value = 0xffffffu;
59
60
61 watchdog_update();
62
63 hw_set_bits(&watchdog_hw->ctrl, WATCHDOG_CTRL_ENABLE_BITS);
64 }
RP2040 Datasheet
4.7. Watchdog 566