Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.5. DMA
- 2.6. Memory
- 2.7. Boot Sequence
- 2.8. Bootrom
- 2.9. Power Supplies
- 2.10. Core Supply Regulator
- 2.11. Power Control
- 2.12. Chip-Level Reset
- 2.13. Power-On State Machine
- 2.14. Subsystem Resets
- 2.15. Clocks
- 2.16. Crystal Oscillator (XOSC)
- 2.17. Ring Oscillator (ROSC)
- 2.18. PLL
- 2.19. GPIO
- 2.20. Sysinfo
- 2.21. Syscfg
- 2.22. TBMAN
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. UART
- 4.3. I2C
- 4.3.1. Features
- 4.3.2. IP Configuration
- 4.3.3. I2C Overview
- 4.3.4. I2C Terminology
- 4.3.5. I2C Behaviour
- 4.3.6. I2C Protocols
- 4.3.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.3.8. Multiple Master Arbitration
- 4.3.9. Clock Synchronization
- 4.3.10. Operation Modes
- 4.3.11. Spike Suppression
- 4.3.12. Fast Mode Plus Operation
- 4.3.13. Bus Clear Feature
- 4.3.14. IC_CLK Frequency Configuration
- 4.3.15. DMA Controller Interface
- 4.3.16. Operation of Interrupt Registers
- 4.3.17. List of Registers
- 4.4. SPI
- 4.5. PWM
- 4.6. Timer
- 4.7. Watchdog
- 4.8. RTC
- 4.9. ADC and Temperature Sensor
- 4.10. SSI
- 4.10.1. Overview
- 4.10.2. Features
- 4.10.3. IP Modifications
- 4.10.4. Clock Ratios
- 4.10.5. Transmit and Receive FIFO Buffers
- 4.10.6. 32-Bit Frame Size Support
- 4.10.7. SSI Interrupts
- 4.10.8. Transfer Modes
- 4.10.9. Operation Modes
- 4.10.10. Partner Connection Interfaces
- 4.10.11. DMA Controller Interface
- 4.10.12. APB Interface
- 4.10.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
- Appendix C: Documentation Release History
Offset Name Info
0x14 SCRATCH2 Scratch register
0x18 SCRATCH3 Scratch register
0x1c SCRATCH4 Scratch register
0x20 SCRATCH5 Scratch register
0x24 SCRATCH6 Scratch register
0x28 SCRATCH7 Scratch register
0x2c TICK Controls the tick generator
WATCHDOG: CTRL Register
Offset: 0x00
Description
Watchdog control
The rst_wdsel register determines which subsystems are reset when the watchdog is triggered.
The watchdog can be triggered in software.
Table 556. CTRL
Register
Bits Name Description Type Reset
31 TRIGGER Trigger a watchdog reset SC 0x0
30 ENABLE When not enabled the watchdog timer is paused RW 0x0
29:27 Reserved. - - -
26 PAUSE_DBG1 Pause the watchdog timer when processor 1 is in debug
mode
RW 0x1
25 PAUSE_DBG0 Pause the watchdog timer when processor 0 is in debug
mode
RW 0x1
24 PAUSE_JTAG Pause the watchdog timer when JTAG is accessing the
bus fabric
RW 0x1
23:0 TIME Indicates the number of ticks / 2 (see errata RP2040-E1)
before a watchdog reset will be triggered
RO 0x000000
WATCHDOG: LOAD Register
Offset: 0x04
Table 557. LOAD
Register
Bits Description Type Reset
31:24 Reserved. - -
23:0 Load the watchdog timer. The maximum setting is 0xffffff which corresponds
to 0xffffff / 2 ticks before triggering a watchdog reset (see errata RP2040-E1).
WF 0x000000
WATCHDOG: REASON Register
Offset: 0x08
Description
Logs the reason for the last reset. Both bits are zero for the case of a hardware reset.
RP2040 Datasheet
4.7. Watchdog 568