Datasheet

Table 60.
INTERP0_ACCUM0_AD
D Register
Bits Description Type Reset
31:24 Reserved. - -
23:0 Values written here are atomically added to ACCUM0
Reading yields lane 0’s raw shift and mask value (BASE0 not added).
RW 0x000000
SIO: INTERP0_ACCUM1_ADD Register
Offset: 0x0b8
Table 61.
INTERP0_ACCUM1_AD
D Register
Bits Description Type Reset
31:24 Reserved. - -
23:0 Values written here are atomically added to ACCUM1
Reading yields lane 1’s raw shift and mask value (BASE1 not added).
RW 0x000000
SIO: INTERP0_BASE_1AND0 Register
Offset: 0x0bc
Table 62.
INTERP0_BASE_1AND
0 Register
Bits Description Type Reset
31:0 On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.
Each half is sign-extended to 32 bits if that lane’s SIGNED flag is set.
WO 0x00000000
SIO: INTERP1_ACCUM0 Register
Offset: 0x0c0
Table 63.
INTERP1_ACCUM0
Register
Bits Description Type Reset
31:0 Read/write access to accumulator 0 RW 0x00000000
SIO: INTERP1_ACCUM1 Register
Offset: 0x0c4
Table 64.
INTERP1_ACCUM1
Register
Bits Description Type Reset
31:0 Read/write access to accumulator 1 RW 0x00000000
SIO: INTERP1_BASE0 Register
Offset: 0x0c8
Table 65.
INTERP1_BASE0
Register
Bits Description Type Reset
31:0 Read/write access to BASE0 register. RW 0x00000000
SIO: INTERP1_BASE1 Register
Offset: 0x0cc
RP2040 Datasheet
2.3. Processor subsystem 56