Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.5. DMA
- 2.6. Memory
- 2.7. Boot Sequence
- 2.8. Bootrom
- 2.9. Power Supplies
- 2.10. Core Supply Regulator
- 2.11. Power Control
- 2.12. Chip-Level Reset
- 2.13. Power-On State Machine
- 2.14. Subsystem Resets
- 2.15. Clocks
- 2.16. Crystal Oscillator (XOSC)
- 2.17. Ring Oscillator (ROSC)
- 2.18. PLL
- 2.19. GPIO
- 2.20. Sysinfo
- 2.21. Syscfg
- 2.22. TBMAN
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. UART
- 4.3. I2C
- 4.3.1. Features
- 4.3.2. IP Configuration
- 4.3.3. I2C Overview
- 4.3.4. I2C Terminology
- 4.3.5. I2C Behaviour
- 4.3.6. I2C Protocols
- 4.3.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.3.8. Multiple Master Arbitration
- 4.3.9. Clock Synchronization
- 4.3.10. Operation Modes
- 4.3.11. Spike Suppression
- 4.3.12. Fast Mode Plus Operation
- 4.3.13. Bus Clear Feature
- 4.3.14. IC_CLK Frequency Configuration
- 4.3.15. DMA Controller Interface
- 4.3.16. Operation of Interrupt Registers
- 4.3.17. List of Registers
- 4.4. SPI
- 4.5. PWM
- 4.6. Timer
- 4.7. Watchdog
- 4.8. RTC
- 4.9. ADC and Temperature Sensor
- 4.10. SSI
- 4.10.1. Overview
- 4.10.2. Features
- 4.10.3. IP Modifications
- 4.10.4. Clock Ratios
- 4.10.5. Transmit and Receive FIFO Buffers
- 4.10.6. 32-Bit Frame Size Support
- 4.10.7. SSI Interrupts
- 4.10.8. Transfer Modes
- 4.10.9. Operation Modes
- 4.10.10. Partner Connection Interfaces
- 4.10.11. DMA Controller Interface
- 4.10.12. APB Interface
- 4.10.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
- Appendix C: Documentation Release History
NOTE
All RTC register reads and writes are done from the processor clock domain clk_sys. All data are synchronised back
and forth between the domains. Writing to the RTC will take 2 clk_rtc clock periods to arrive, additional to the clk_sys
domain. This should be taken into account especially when the reference is slow (e.g. 1 Hz).
4.8.5. Programmer’s Model
There are three setup tasks:
•
Set the 1 sec reference
•
Set the clock
•
Set an alarm
4.8.5.1. Configuring the 1 second reference clock:
Select the source for clk_rtc. This is done outside the RTC registers (see Section 4.8.4).
SDK: https://github.com/raspberrypi/pico-sdk/tree/master/src/rp2_common/hardware_rtc/rtc.c Lines 22 - 40
22 void rtc_init(void) {
23 // Get clk_rtc freq and make sure it is running
24 uint rtc_freq = clock_get_hz(clk_rtc);
25 assert(rtc_freq != 0);
26
27 // Take rtc out of reset now that we know clk_rtc is running
28 reset_block(RESETS_RESET_RTC_BITS);
29 unreset_block_wait(RESETS_RESET_RTC_BITS);
30
31 // Set up the 1 second divider.
32 // If rtc_freq is 400 then clkdiv_m1 should be 399
33 rtc_freq -= 1;
34
35 // Check the freq is not too big to divide
36 assert(rtc_freq <= RTC_CLKDIV_M1_BITS);
37
38 // Write divide value
39 rtc_hw->clkdiv_m1 = rtc_freq;
40 }
4.8.5.2. Setting up the clock
SDK: https://github.com/raspberrypi/pico-sdk/tree/master/src/rp2_common/hardware_rtc/rtc.c Lines 55 - 86
55 bool rtc_set_datetime(datetime_t *t) {
56 if (!valid_datetime(t)) {
57 return false;
58 }
59
60 // Disable RTC
61 rtc_hw->ctrl = 0;
62 // Wait while it is still active
63 while (rtc_running()) {
64 tight_loop_contents();
RP2040 Datasheet
4.8. RTC 571