Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.5. DMA
- 2.6. Memory
- 2.7. Boot Sequence
- 2.8. Bootrom
- 2.9. Power Supplies
- 2.10. Core Supply Regulator
- 2.11. Power Control
- 2.12. Chip-Level Reset
- 2.13. Power-On State Machine
- 2.14. Subsystem Resets
- 2.15. Clocks
- 2.16. Crystal Oscillator (XOSC)
- 2.17. Ring Oscillator (ROSC)
- 2.18. PLL
- 2.19. GPIO
- 2.20. Sysinfo
- 2.21. Syscfg
- 2.22. TBMAN
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. UART
- 4.3. I2C
- 4.3.1. Features
- 4.3.2. IP Configuration
- 4.3.3. I2C Overview
- 4.3.4. I2C Terminology
- 4.3.5. I2C Behaviour
- 4.3.6. I2C Protocols
- 4.3.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.3.8. Multiple Master Arbitration
- 4.3.9. Clock Synchronization
- 4.3.10. Operation Modes
- 4.3.11. Spike Suppression
- 4.3.12. Fast Mode Plus Operation
- 4.3.13. Bus Clear Feature
- 4.3.14. IC_CLK Frequency Configuration
- 4.3.15. DMA Controller Interface
- 4.3.16. Operation of Interrupt Registers
- 4.3.17. List of Registers
- 4.4. SPI
- 4.5. PWM
- 4.6. Timer
- 4.7. Watchdog
- 4.8. RTC
- 4.9. ADC and Temperature Sensor
- 4.10. SSI
- 4.10.1. Overview
- 4.10.2. Features
- 4.10.3. IP Modifications
- 4.10.4. Clock Ratios
- 4.10.5. Transmit and Receive FIFO Buffers
- 4.10.6. 32-Bit Frame Size Support
- 4.10.7. SSI Interrupts
- 4.10.8. Transfer Modes
- 4.10.9. Operation Modes
- 4.10.10. Partner Connection Interfaces
- 4.10.11. DMA Controller Interface
- 4.10.12. APB Interface
- 4.10.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
- Appendix C: Documentation Release History
•
Sleep mode, where the processors are asleep and the unused clocks in the chip are stopped (see Section 2.15.3.5)
•
Dormant mode, where all clocks in the chip are stopped
The RTC can wake the chip up from both of these modes. In sleep mode, RP2040 can be configured such that only
clk_rtc (a slow RTC reference clock) is running, as well as a small amount of logic that allows the processor to wake
back up. The processor is woken from sleep mode when the RTC alarm interrupt fires. See Section 2.11.5.1 for more
information.
To wake the chip from dormant mode:
•
the RTC must be configured to use an external reference clock (supplied by a GPIO pin)
•
Set up the RTC to run on an external reference
•
If the processor is running off the PLL, change it to run from XOSC/ROSC
•
Turn off the PLLs
•
Set up the RTC with the desired wake up time (one off, or recurring)
•
(optionally) power down most memories
•
Invoke DORMANT mode (see Section 2.16, Section 2.17, and Section 2.11.5.2 for more information)
4.8.6. List of Registers
The RTC registers start at a base address of 0x4005c000 (defined as RTC_BASE in SDK).
Table 562. List of RTC
registers
Offset Name Info
0x00 CLKDIV_M1 Divider minus 1 for the 1 second counter. Safe to change the
value when RTC is not enabled.
0x04 SETUP_0 RTC setup register 0
0x08 SETUP_1 RTC setup register 1
0x0c CTRL RTC Control and status
0x10 IRQ_SETUP_0 Interrupt setup register 0
0x14 IRQ_SETUP_1 Interrupt setup register 1
0x18 RTC_1 RTC register 1.
0x1c RTC_0 RTC register 0
Read this before RTC 1!
0x20 INTR Raw Interrupts
0x24 INTE Interrupt Enable
0x28 INTF Interrupt Force
0x2c INTS Interrupt status after masking & forcing
RTC: CLKDIV_M1 Register
Offset: 0x00
RP2040 Datasheet
4.8. RTC 574