Datasheet

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Table Of Contents

Table 66.

INTERP1_BASE1

Bits Description Type Reset

31:0 Read/write access to BASE1 register. RW 0x00000000

SIO: INTERP1_BASE2 Register

Offset: 0x0d0

Table 67.

INTERP1_BASE2

Bits Description Type Reset

31:0 Read/write access to BASE2 register. RW 0x00000000

SIO: INTERP1_POP_LANE0 Register

Offset: 0x0d4

Table 68.

INTERP1_POP_LANE0

Bits Description Type Reset

31:0 Read LANE0 result, and simultaneously write lane results to both

accumulators (POP).

RO 0x00000000

SIO: INTERP1_POP_LANE1 Register

Offset: 0x0d8

Table 69.

INTERP1_POP_LANE1

Bits Description Type Reset

31:0 Read LANE1 result, and simultaneously write lane results to both

accumulators (POP).

RO 0x00000000

SIO: INTERP1_POP_FULL Register

Offset: 0x0dc

Table 70.

INTERP1_POP_FULL

Bits Description Type Reset

31:0 Read FULL result, and simultaneously write lane results to both accumulators

(POP).

RO 0x00000000

SIO: INTERP1_PEEK_LANE0 Register

Offset: 0x0e0

Table 71.

INTERP1_PEEK_LANE

0 Register

Bits Description Type Reset

31:0 Read LANE0 result, without altering any internal state (PEEK). RO 0x00000000

SIO: INTERP1_PEEK_LANE1 Register

Offset: 0x0e4

Table 72.

INTERP1_PEEK_LANE

1 Register

Bits Description Type Reset

31:0 Read LANE1 result, without altering any internal state (PEEK). RO 0x00000000

SIO: INTERP1_PEEK_FULL Register

Offset: 0x0e8

RP2040 Datasheet

2.3. Processor subsystem 57