Datasheet

4.9.2. SAR ADC
The SAR ADC (Successive Approximation Register Analogue to Digital Converter) is a combination of digital controller,
and analogue circuit as show in Figure 115.
Figure 115. SAR ADC
Block diagram
The ADC requires a 48MHz clock (clk_adc), which could come from the USB PLL. Capturing a sample takes 96 clock
cycles (96 x 1 / 48MHz) = 2 μs per sample (500kS/s). The clock must be set up correctly before enabling the ADC.
Once the ADC block is provided with a clock, and its reset has been removed, writing a 1 to CS.EN will start a short
internal power-up sequence for the ADC’s analogue hardware. After a few clock cycles, CS.READY will go high,
indicating the ADC is ready to start its first conversion.
The ADC can be disabled again at any time by clearing CS.EN, to save power. CS.EN does not enable the temperature
sensor bias source (see Section 4.9.5). This is controlled separately.
The ADC input is capacitive, and when sampling, it places about 1pF across the input (there will be additional
capacitance from outside the ADC, such as packaging and PCB routing, to add to this). The effective impedance, even
when sampling at 500kS/s, is over 100kΩ, and for dc measurements there should be no need to buffer.
4.9.2.1. One-shot Sample
Writing a 1 to CS.START_ONCE will immediately start a new conversion. CS.READY will go low, to show that a
conversion is currently in progress. After 96 cycles of clk_adc, CS.READY will go high. The 12-bit conversion result is
available in RESULT.
The ADC input to be sampled is selected by writing to CS.AINSEL, any time before the conversion starts. An AINSEL
value of 0…3 selects the ADC input on GPIO 26…29. AINSEL of 4 selects the internal temperature sensor.

NOTE
No settling time is required when switching AINSEL.
4.9.2.2. Free-running Sampling
When CS.START_MANY is set,the ADC will automatically start new conversions at regular intervals. The most recent
conversion result is always available in RESULT, but for IRQ or DMA driven streaming of samples, the ADC FIFO must be
enabled (Section 4.9.2.4).
By default (DIV = 0), new conversions start immediately upon the previous conversion finishing, so a new sample is
produced every 96 cycles. At a clock frequency of 48 MHz, this produces 500 kS/s.
Setting DIV.INT to some positive value n will trigger the ADC once per n + 1 cycles, though the ADC ignores this if a
conversion is currently in progress, so generally n will be >= 96. For example, setting DIV.INT to 47999 will run the ADC
at 1 kS/s, if running from a 48 MHz clock.
The pacing timer supports fractional-rate division (first order delta sigma). When setting DIV.FRAC to a nonzero value,
RP2040 Datasheet
4.9. ADC and Temperature Sensor 580