Datasheet


CAUTION
Conversion errors produce undefined results, and the corresponding sample should be discarded. They indicate that
the comparison of one or more bits failed to complete in the time allowed. Normally this is caused by comparator
metastability, i.e. the closer to the comparator threshold the input signal is, the longer it will take to make a decision.
The high gain of the comparator reduces the probability that no decision is made.
4.9.2.5. DMA
The RP2040 DMA (Section 2.5) can fetch ADC samples from the sample FIFO, by performing a normal memory-mapped
read on the FIFO register, paced by the ADC_DREQ system data request signal. The following must be considered:
•
The sample FIFO must be enabled (FCS.EN) so that samples are written to it; the FIFO is disabled by default so
that it does not inadvertently fill when the ADC is used for one-shot conversions.
•
The ADC’s data request handshake (DREQ) must be enabled, via FCS.DREQ_EN.
•
The DMA channel used for the transfer must select the DREQ_ADC data request signal (Section 2.5.3.1).
•
The threshold for DREQ assertion (FCS.THRESH) should be set to 1, so that the DMA transfers as soon as a single
sample is present in the FIFO. Note this is also the threshold used for IRQ assertion, so non-DMA use cases might
prefer a higher value for less frequent interrupts.
•
If the DMA transfer size is set to 8 bits, so that the DMA transfers to a byte array in memory, FCS.SHIFT must also
be set, to pre-shift the FIFO samples to 8 bits of significance.
•
If multiple input channels are to be sampled, CS.RROBIN contains a 5-bit mask of those channels (4 external inputs
plus temperature sensor). Additionally CS.AINSEL must select the channel for the first sample.
•
The ADC sample rate (Section 4.9.2.2) should be configured before starting the ADC.
Once the ADC is suitably configured, the DMA channel should be started first, and the ADC conversion should be started
second, via CS.START_MANY. Once the DMA completes, the ADC can be halted, or a new DMA transfer promptly
started. After clearing CS.START_MANY to halt the ADC, software should also poll CS.READY to make sure the last
conversion has finished, and then drain any stray samples from the FIFO.
4.9.2.6. Interrupts
An interrupt can be generated when the FIFO level reaches a configurable threshold FCS.THRESH. The interrupt output
must be enabled via INTE.
Status can be read from INTS. The interrupt is cleared by draining the FIFO to a level lower than FCS.THRESH.
4.9.2.7. Supply
The ADC supply is separated out on its own pin to allow noise filtering.
4.9.3. ADC ENOB
The ADC was characterised and the ENOB of the ADC was measured. Testing was carried out at room temperature
across silicon lots, with tests being done on 3 typical (tt) as well as 3 fast (ff) and 3 slow (ss) corner RP2040 devices.
The typical, minimum, and maximum values in Table 576 reflect the silicon used in the testing.
Table 575. Parameters
used during the
testing.
Parameter Value
Sample rate 250 Ksps
FFT window 5 term Blackman-Harris
RP2040 Datasheet
4.9. ADC and Temperature Sensor 582