Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.5. DMA
- 2.6. Memory
- 2.7. Boot Sequence
- 2.8. Bootrom
- 2.9. Power Supplies
- 2.10. Core Supply Regulator
- 2.11. Power Control
- 2.12. Chip-Level Reset
- 2.13. Power-On State Machine
- 2.14. Subsystem Resets
- 2.15. Clocks
- 2.16. Crystal Oscillator (XOSC)
- 2.17. Ring Oscillator (ROSC)
- 2.18. PLL
- 2.19. GPIO
- 2.20. Sysinfo
- 2.21. Syscfg
- 2.22. TBMAN
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. UART
- 4.3. I2C
- 4.3.1. Features
- 4.3.2. IP Configuration
- 4.3.3. I2C Overview
- 4.3.4. I2C Terminology
- 4.3.5. I2C Behaviour
- 4.3.6. I2C Protocols
- 4.3.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.3.8. Multiple Master Arbitration
- 4.3.9. Clock Synchronization
- 4.3.10. Operation Modes
- 4.3.11. Spike Suppression
- 4.3.12. Fast Mode Plus Operation
- 4.3.13. Bus Clear Feature
- 4.3.14. IC_CLK Frequency Configuration
- 4.3.15. DMA Controller Interface
- 4.3.16. Operation of Interrupt Registers
- 4.3.17. List of Registers
- 4.4. SPI
- 4.5. PWM
- 4.6. Timer
- 4.7. Watchdog
- 4.8. RTC
- 4.9. ADC and Temperature Sensor
- 4.10. SSI
- 4.10.1. Overview
- 4.10.2. Features
- 4.10.3. IP Modifications
- 4.10.4. Clock Ratios
- 4.10.5. Transmit and Receive FIFO Buffers
- 4.10.6. 32-Bit Frame Size Support
- 4.10.7. SSI Interrupts
- 4.10.8. Transfer Modes
- 4.10.9. Operation Modes
- 4.10.10. Partner Connection Interfaces
- 4.10.11. DMA Controller Interface
- 4.10.12. APB Interface
- 4.10.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
- Appendix C: Documentation Release History
Parameter Value
FFT bins 4,096
FFT averaging none
Input level min 1
Input level max 4,094
Input frequency 997 Hz
It should be noted that THD is normally calculated using the first 5 or 6 harmonics. However as INL/DNL errors (see
Section 4.9.4) create more than this, the first 30 peaks are used. This makes the THD value slightly worse, but more
representative of reality.
Table 576. Results for
various parts tested
(fast, slow, and
typical).
Min Typical Max
THD
1
-55.6dB 55dB -54.4dB
SNR 60.9dB 61.5dB 62.0dB
SFDR 59.2dB 59.9dB 60.5dB
SINAD 53.6dB 54.0dB 54.6dB
ENOB 8.6 8.7 8.8
1
As the INL creates a large number of harmonics, the highest 30 peaks were used. This is different from conventional
calculations of THD.
IMPORTANT
Testing was carried out using a board with a low-noise on-board voltage reference as, when characterising the ADC,
it is important that there are no other noise sources affecting the measurements.
4.9.4. INL and DNL
Integral Non-Linearity (INL) and Differential Non-Linearity (DNL) are used to measure the error of the quantisation of the
incoming signal that the ADC generates. In an ideal ADC the input-to-output transfer function should have a linear
quantised transfer between the analogue input signal and the digitised output signal. The RP2040 ADC INL values for
each binary result are shown in Figure 116, illustrating that the error is a sawtooth rather than the expected curve.
Figure 116. ATE
machine results for
INL (RP2040).
RP2040 Datasheet
4.9. ADC and Temperature Sensor 583